Digital noise filter

Details Digital noise filter Digital noise filter

2011-05-31

2011-05-31

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S026000, C326S028000, C326S094000

Reexamination Certificate

active

07952391

ABSTRACT:
A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.

REFERENCES:
patent: 7868662 (2011-01-01), Kinugasa et al.
patent: 2009/0313313 (2009-12-01), Yokokawa et al.
patent: 2004-200837 (A) (2004-07-01), None

Affiliated with

Also associated with

Rating

Digital noise filter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital noise filter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital noise filter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2667292