Digital multiplier employing CMOS transistors

Details Digital multiplier employing CMOS transistors Digital multiplier employing CMOS transistors

1990-02-01

1992-03-10

Malzahn, David H.

Boots, shoes, and leggings

36471509, G06F 752

Patent

active

050954571

ABSTRACT:
A digital multiplier for multiplying a binary N bit multiplicand by a binary N bit multiplier. The digital multiplier comprises a plurality of AND gates in which each digit of the mutliplicand is multiplied by each digit of the multiplier. The outputs of the AND gates represent partial products which are then arranged corresponding to each digit of the multiplier. The digital multiplier further comprises a plurality of 1's counters for receiving in parallel all partial products, except the least significant digit of the multiplier, and any carries propagated from an adjacent counter, and for counting the number of "1" in the resultant values. The 1's counters output the least significant bit as the final products, and propagate the remaining bits to the next 1's counter.

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patent: 3723715 (1973-03-01), Chen et al.
patent: 3795880 (1974-03-01), Singh et al.
patent: 4607176 (1986-08-01), Burrows et al.
patent: 4891782 (1990-01-01), Johnson
patent: 5016211 (1971-05-01), Jeong
Crosthwait et al., "Column Toter PLA" IBM Tech. Disclosure Bulletin, vol. 22, No. 6 Nov. 1979, pp. 2339-2341.

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