Digital modulation circuit and digital demodulation circuit

Details Digital modulation circuit and digital demodulation circuit Digital modulation circuit and digital demodulation circuit

1996-08-02

2000-06-20

Grant, William

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714755, 714753, 714762, 370203, 370330, 370329, 370335, 704229, 704205, 386 46, 386 81, H03M 1300

Patent

active

060790415

ABSTRACT:
A digital modulation circuit which minimizes a DC component of an NRZI modulated code sequence while setting the T.sub.max and T.sub.W not to be varied. An m-n coding mode is determined for each data block composed of the predetermined number of m-bit datawords. That is, an m-n coding mode which minimizes the absolute value of the DSV is selected and the selected m-n coding mode is utilized for the m-n coding of the current data block. The code indicating the selected m-n coding mode is multiplexed to the m-n coded current block. An m--m mapping table is also determined for each data block. That is, such an m--m mapping table that minimizes the absolute value of the DSV is selected and the selected m--m mapping table is utilized for the m--m translation of the current data block. Then, the m--m mapped data block is m-n translated into a code block composed of the same number of n-bit codewords by utilizing the single m-n translation table.

REFERENCES:
patent: 4499454 (1985-02-01), Shimada
patent: 4541093 (1985-09-01), Furuya et al.
patent: 5508701 (1996-04-01), Nose et al.

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