Digital memory with reset/preset capabilities

Details Digital memory with reset/preset capabilities Digital memory with reset/preset capabilities

1986-08-28

1989-02-14

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365218, 365190, 357 44, 357 48, G11C 1140

Patent

active

048051497

ABSTRACT:
A digital memory characterized by a plurality of memory cells arranged into a matrix having rows and columns; a row activation circuit for concurrently activating all of the rows of the matrix; and column activation means for concurrently applying either a reset signal or a preset signal to the columns of the matrix. The column activation circuit can include a plurality of digital switches coupled to reset and preset lines associated with each column of the matrix; and reset/preset logic which control the digital switches to selectively couple the reset and preset lines to a constant current source. A complementary, multi-emitter flip-flop memory cell is formed on a semiconductor substrate and includes "riser" portions.

REFERENCES:
patent: 4172291 (1979-10-01), Owens et al.
patent: 4393473 (1983-07-01), Rufford
patent: 4408306 (1983-10-01), Kuo
patent: 4440712 (1983-08-01), O'Connor
patent: 4489404 (1984-12-01), Yasuoka
patent: 4567578 (1986-01-01), Cohen et al.
patent: 4580244 (1986-04-01), Birrittella
patent: 4701883 (1987-10-01), Wrathall et al.

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