Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2001-08-17
2002-12-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S184000, C365S189011, C365S189070
Reexamination Certificate
active
06490218
ABSTRACT:
BACKGROUND
The present invention relates to digital memory arrays of the type that include anti-fuse layers within the individual memory cells, and in particular to such arrays that provide high-density data storage.
Memory arrays that use anti-fuse layers to store digital data are well known to those skilled in the art. Such arrays operate as write-once memories, and they are generally field programmable. U.S. Pat. No. 6,034,882 and U.S. patent application Ser. No. 09/560,626, both assigned to the assignee of the present invention, disclose two such memory arrays.
The memory arrays of these documents include memory cells that are arranged in three-dimensional arrays. Each memory cell includes a diode and an anti-fuse layer. The anti-fuse layer initially is insulating, and it blocks forward current through the memory cell. The memory cell can be programmed by passing a write current through the memory cell to disrupt the anti-fuse layer, thereby lowering the resistance of the memory cell. The contents of the memory cell can be read as a logic 1 if the memory cell resistance is in a lower range, indicating that the anti-fuse layer has been disrupted, and as a logic 0 if the resistance is at the much higher initial level.
Though the memory arrays discussed above provide high-density, low-cost, write-once memories, further improvements to the data storage density of the array would further lower cost.
SUMMARY
By way of general introduction, the preferred embodiments described below generate two or more write signals that differ in power level. Depending upon which of the write signals is applied to a particular memory cell, the anti-fuse layer of that memory cell is disrupted to a varying extent, and the electrical resistance of that memory cell is programmed accordingly. The contents of the memory cell can be read by applying a voltage across the memory cell and comparing the resulting current with two or more thresholds. In this way, more than two logical states are stored in each memory cell of the array.
The foregoing paragraphs have been provided by way of general introduction, and they should not be used to limit the scope of the following claims.
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U.S. patent application Ser. No. 09/560,626, filed Apr. 28, 2000, N. Johan Knall.
Knall N. Johan
Vyvoda Michael A.
Brinks Hofer Gilson & Lione
Matrix Semiconductor Inc.
Nelms David
Pham Ly Duy
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