Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2000-03-27
2001-03-27
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S189050
Reexamination Certificate
active
06208562
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates, in general, to a digital memory and to a method of operating a digital memory.
For dynamic memories (DRAMs), operating modes that can be stipulated by the memory manufacturer are based on a JEDEC standard. The JEDEC standard merely defines how to change from a normal operating mode to additional operating modes. Often, these additional operating modes are manufacturer-specific test operating modes. According to the JEDEC standard, a change into these additional operating modes can be performed by applying prescribed signal combinations to the standard external connections of the DRAM.
When a memory is operating, and particularly, when the memory is being tested, it is desirable to be able to establish whether an intentional change of operating modes has actually taken place, or whether an unintentional change has occurred by chance. However, the presented problem is that the number of external connections of a DRAM is limited, so that, under some circumstances, none of the connections can be used to output an appropriate status signal that can give information about the particular operating mode.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory and a corresponding method of operating the memory which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type in such a way that different operating modes can be recognized from outside the memory without providing or using additional external connections.
With the foregoing and other objects in view there is provided, in accordance with the invention, a digital memory that has data lines for writing data to the memory and for reading data from the memory, and address lines for addressing the memory during reading and writing. It also has at least one switching unit which, in an active state, inverts signals on at least one of the data lines or on at least one of the address lines and which, in an inactive state, leaves the signals unchanged. In a first operating mode of the memory, the switching unit is in the same state (active or inactive) both for writing and for reading. In contrast, in a second operating mode, the switching unit is in respectively opposite states for writing and for reading.
Consequently, in the first operating mode, the memory behaves like a conventional memory, in which stored data is read in the same state as that with which it was written to the memory. As far as the second operating mode is concerned, two embodiments of the invention are distinguishable, which have no equivalents in conventional memories. In the first embodiment, the signal on one or more of the data lines is inverted only in the second operating mode either for writing or for reading. By comparing the written data with the read data it is then easy to establish, from outside the memory, which operating mode the memory is in.
In the second embodiment of the memory, the data on at least one of the address lines is inverted in the second operating mode either for writing or for reading. This means that, for writing and reading in the second operating mode, different memory cells of the memory are addressed in each case using the same external address. If mutually complementary data has previously been written to these different memory cells, it is again possible to detect a change to the second operating mode from outside the memory without any great complexity.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of operating a digital memory. In a first operating mode of the digital memory, when an address is applied during a read operation, data which has previously been written under this address is read with an unchanged logic state. In contrast, in a second operating mode, when an address is applied during a read operation, data is read which is the inverse of the data previously written under this external address.
According to a first embodiment of the method of operation, in the second operating mode, data is inverted either for writing or for reading.
According to a second embodiment of the method of operation, in the second operating mode, when an address is applied during a read operation, data is read from different memory cells than were previously addressed with this address for writing. In contrast, in the first operating mode, for writing and reading, the same address is used to address the same respective memory cells. In one development of this second embodiment of the method of operation, data having a first logic state is written to a first memory area of the memory, and data having a second logic state is written to a second memory area of the memory. Then, in the second operating mode, data is read from the second memory area during a read operation as a result of applying an address associated with the first memory area during a write operation. This achieves the effect that, in the second operating mode, data which is the inverse of that previously written to the memory under the same external address is read.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a digital memory and method of operation for a digital memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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Johnson Bret
Zibert Martin
Greenberg Laurence A.
Infineon - Technologies AG
Le Vu A.
Lerner Herbert L.
Stemer Werner H.
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