Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
2001-08-03
2003-09-30
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S027000, C326S082000
Reexamination Certificate
active
06628139
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital logic devices used in integrated circuits. More specifically, the present invention relates to digital logic gates, such as inverters, buffers, NAND gates and NOR gates, with extremely skewed trip points and reset circuitry for propagating fast signal edges. Additionally, the present invention relates to circuits, substrates, systems and methods incorporating digital logic gates with extremely skewed trip points.
BACKGROUND OF THE INVENTION
Advances in semiconductor manufacturing technologies have allowed digital integrated circuit designers to place several million transistors interconnected on a single substrate. Concurrently, advances in computer architecture and particularly processor architecture have driven ever-shorter cycle times. These advances in semiconductor manufacturing and processor architecture have forced digital integrated circuit designers to consider new ways of implementing basic circuit functions, particularly for low-power and high-speed applications.
In metal oxide semiconductor (MOS) devices, the speed of operation is limited by the resistance of a given MOS transistor driving the capacitance (input load) of the next MOS transistor. The output current of a MOS transistor is proportional to its channel width. Thus, if a narrow channel transistor is used to drive a high capacitance load, a relatively long delay results. To reduce this delay in digital circuits, a series of cascaded inverters is frequently used. For example, see U.S. Pat. No. 5,343,090, explicitly incorporated herein by reference for all purposes.
Increasing clock frequency is another approach to reducing cycle times. However, by increasing clock frequencies, fewer (or shorter) logic gate delays are permitted during each clock cycle. To accommodate this need for shorter gate delays, a number of circuit technologies have been implemented for high-speed operation.
Static full complementary metal-oxide semiconductor (CMOS) logic provides two types of transistors, a p-type transistor (PMOS) and an n-type transistor (NMOS). The terms “device” and “structure” used herein to describe CMOS logic include PMOS and NMOS transistors.
FIG. 1
illustrates a conventional inverter
100
constructed from CMOS logic.
FIG. 2
is a timing diagram for conventional inverter
100
illustrating input signal IN and output signal OUT. Additionally, input gate loading is shared between devices that generate rising and falling edges of a conventional CMOS inverter.
Dynamic logic structures, e.g., domino logic devices, propagate signal edges much quicker than static full CMOS logic. Domino logic refers to a circuit arrangement in which there are several series-coupled logic stages having precharged output nodes. The output node of an individual logic stage is precharged to a first logic level. Logic signals are then applied such that, depending on the logic function being implemented and the state of the various input signals, the output node can be switched to a second logic level. As each domino stage in the chain evaluates, the output of the next domino stage may be enabled to switch. However, problems with domino logic include the necessity for precharge circuitry and charge sharing induced noise.
There is a need in the art for digital logic devices capable of propagating selected signal edges more rapidly than conventional CMOS inverters, with virtually all of the input gate loading (capacitance) devoted to the devices that generate a fast edge being propagated, and without the charge sharing induced noise problem associated with domino logic.
SUMMARY OF THE INVENTION
The invention includes digital logic devices with extremely skewed trip points and reset circuitry, referred to herein as “skewed logic devices,” for rapidly propagating signal edges. Embodiments of skewed logic devices according to the present invention include inverters, buffers, NAND gates and NOR gates. The invention also includes circuits, substrates, systems and methods including skewed logic devices as disclosed herein. Each embodiment of a skewed logic device of the present invention is configured to rapidly propagate either a rising edge or falling edge of an output signal, i.e., the “fast” edge, with a delay comparable to that of domino logic. The other corresponding, “slow” edge propagates with a delay of about 2 to 4 ordinary gate delays.
An advantage of the skewed logic devices of the present invention over conventional CMOS inverters is rapid edge propagation. Another advantage is that virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks described herein are buffered by at least 2 gates, thus reducing loading seen by the input or the output of the skewed logic device associated with conventional reset circuitry.
An embodiment of a skewed inverter rising logic device of the present invention for rapidly propagating a rising edge of an output signal includes a fast inverter rising having a large p
channel width ratio for receiving an input signal and rapidly propagating a rising edge onto the output signal in response to receiving a falling edge on the input signal. A skewed inverter rising logic device further includes a pull-down reset network connected in parallel with the fast inverter rising for resetting the output signal after the rising edge has been propagated onto the output signal, and a feedback delay circuit connected in parallel with the pull-down reset network for delaying and returning the output signal back to the pull-down reset network.
An embodiment of a skewed inverter falling logic device of the present invention for rapidly propagating a falling edge output signal includes a fast inverter falling having a large n/p channel width ratio for receiving an input signal and rapidly propagating a falling edge onto the output signal in response to receiving a rising edge on the input signal. Skewed inverter falling logic device further includes a pull-up reset network connected in parallel to the fast inverter falling for resetting the output signal after the falling edge has been propagated onto the output signal, and a feedback delay circuit connected in parallel with the pull-up reset network for delaying and returning the output signal to the pull-up reset network.
An embodiment of a skewed buffer rising logic device of the present invention for rapidly propagating a rising edge of an output signal includes a fast inverter falling having a large n/p channel width ratio for receiving a rising edge of an input signal and rapidly propagating a falling edge of an intermediate signal in response thereto and a fast inverter rising having a large p
channel width ratio and in series with the fast inverter falling for receiving the rapidly propagated falling edge of the intermediate signal and rapidly propagated rising edge on the output signal. A skewed buffer rising logic device may further include a reset network coupled to the fast inverter falling and the fast inverter rising for resetting output signals of the fast inverter falling and the fast inverter rising after the rising edge of the output signal has been rapidly propagated, and a feedback delay circuit operably coupled between an output of the fast inverter rising and an input of the reset network for propagating the output signal to the reset network.
An embodiment of a skewed buffer falling logic device of the present invention for rapidly propagating a falling edge of an output signal includes a fast inverter rising having a large p
channel width ratio for receiving a falling edge of an input signal and rapidly propagating a rising edge of an intermediate signal in response thereto and a fast inverter falling having a large n/p channel width ratio and in series with the fast inverter rising for receiving the rapidly propagated rising edge of the intermediate signal and rapidly propagated falling edge on the output signal. A skewed buffer falling logic device may further include a reset network coupled to the fast inverter ri
Gans Dean D.
Porter John D.
Weber Larren G.
Tokar Michael
Tran Anh
TraskBritt
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