Digital locked loop on channel tagged memory requests for...

Details Digital locked loop on channel tagged memory requests for... Digital locked loop on channel tagged memory requests for...

2011-08-09

2011-08-09

Peugh, Brian R (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S154000

Reexamination Certificate

active

07996642

ABSTRACT:
A method and system for performing memory optimization. The method includes receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests; measuring arrival times of the read/write requests assigned to each of the identifiers; determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers; creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests; using the real-time schedule to determine idle periods where none of the read/write requests will be received; and performing opportunistic functions during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch.

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