Digital lock detector for PLL

Details Digital lock detector for PLL Digital lock detector for PLL

2004-08-11

2008-09-09

Ghayour, Mohammad (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C375S375000, C375S376000

Reexamination Certificate

active

07424082

ABSTRACT:
Circuits and methods for detecting a lock condition of a phase-locked loop (PLL) circuit are provided. A frequency divider outputs a clock having a frequency equal to a reference clock frequency divided by N. A counter counts the number (M) of clock edges of a PLL output clock received during a given time interval of the frequency-divided reference clock. When M satisfies a predetermined relationship to N (e.g., M=N), the PLL output clock is locked to the frequency of the reference clock. A phase sampler compares the phases of the PLL output clock, a delayed PLL output clock and either the reference clock or a delayed reference clock. When the phase of the reference clock or delayed reference clock is between the phases of the PLL output clock and the delayed PLL output clock, the PLL output clock is also locked to the phase of the reference clock.

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