Digital line delay using a single port memory

Details Digital line delay using a single port memory Digital line delay using a single port memory

2006-04-18

2006-04-18

Tung, Kee M. (Department: 2671)

Static information storage and retrieval

Read/write circuit

Signals

C345S537000

Reexamination Certificate

active

07031206

ABSTRACT:
An apparatus for delaying video line data between a sending device and a receiving device is provided. The apparatus includes a single port random access memory (“RAM”) and a processing arrangement including a first storage device coupled to the RAM and a second storage device coupled to the RAM.

REFERENCES:
patent: 5537563 (1996-07-01), Guttag et al.
patent: 5608425 (1997-03-01), Movshovich
patent: 5774178 (1998-06-01), Chern et al.
patent: 6118818 (2000-09-01), Min et al.
patent: 2002/0031039 (2002-03-01), Suzuki

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