Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2001-03-29
2002-05-28
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S027000, C326S093000, C326S095000, C326S121000
Reexamination Certificate
active
06396305
ABSTRACT:
TECHNICAL FIELD
This disclosure relates generally to dynamic logic circuits, and in particular but not exclusively, relates to leakage compensation circuits for use in dynamic logic circuits.
BACKGROUND
Dynamic logic circuits are clocked circuits typically used in high-speed applications such as, for example, microprocessors. Typical dynamic logic circuits have two main operating phases, a first (or precharge) phase and a second (or evaluation) phase, defined by the duty cycle of the clock signal. In the precharge phase, the clock signal is at its first phase logic level (e.g., a logic low level), which causes the dynamic circuit to precharge a node of the dynamic circuit to a predetermined voltage level (e.g., the supply voltage VDD). Then when the clock signal transitions to its second phase logic level (e.g., a logic high level), the dynamic circuit selectively discharges the node as a function of the logic state of an input data signal. When the input data signal does not cause the node to be discharged, the node ideally remains charged to the precharged level.
Further, during the evaluation phase, the dynamic circuit generates an output signal having a logic level that is a function of the logic level of the node. The logic level of the output signal is then latched at the end of the evaluation phase.
One shortcoming of such dynamic circuits is that charge may leak from the node. This charge leakage can cause a dynamic circuit to malfunction (e.g., latch the output signal with an incorrect logic level) when the logic level of the input data signal is supposed to cause the node to remain charged during the evaluation phase. In particular, the leakage can undesirably discharge the node to a level that the dynamic circuit detects as a change in logic level, thereby resulting in a circuit failure.
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Ken'ichi Agawa et al; “A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAM's;” Symposium on VLSI Circuits Digest of Technical Papers; 2000; Kawasaki, 212-8520, Japan.
Intel Corporation
Paik Steven S.
Tokar Michael
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