Digital information signal reproducing circuit and digital infor

Details Digital information signal reproducing circuit and digital infor Digital information signal reproducing circuit and digital infor

1996-09-25

1999-08-10

Pham, Chi H.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 327141, 329325, H03D 324, H03D 302, H03L 700

Patent

active

059370203

ABSTRACT:
Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.

REFERENCES:
patent: 4802009 (1989-01-01), Hartmeier
patent: 5075640 (1991-12-01), Miyazawa
patent: 5228035 (1993-07-01), Hirato et al.
patent: 5552942 (1996-09-01), Ziperovich et al.
patent: 5583706 (1996-12-01), Dudley et al.
patent: 5648964 (1997-07-01), Inagaki et al.
patent: 5675620 (1997-10-01), Chen
"Timing Recovery in Digital Synchronous Data Receivers", IEEE Transactions on Communications, vol. COM-24, No. 5, May 1976, pp. 516-531.

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