Digital frequency synthesizer based PLL

Details Digital frequency synthesizer based PLL Digital frequency synthesizer based PLL

2007-06-12

2007-06-12

Tran, Khanh (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

10619488

ABSTRACT:
The present invention provides a phase-locked loop that comprises a divider, a noise-shaped quantizer, a filter, a phase detector and digital loop filter. The divider is used for receiving a reference clock with a substantially fixed period and generating an output clock with a time-varying period. The noise-shaped quantizer is used for quantizing a period control word to a time-varying value in response to the output clock fed from the divider so that the divider generates the output clock by means of dividing the reference clock by the time-varying value. The filter is employed to substantially filter out jitter from the output clock. The phase detector is used for generating a phase error in response to the filtered output clock and an input signal. The digital loop filter is used for generating the period control word in response to the phase error.

REFERENCES:
patent: 5825253 (1998-10-01), Mathe et al.
patent: 6515553 (2003-02-01), Filiol et al.
patent: 6700446 (2004-03-01), Ke
patent: 6927716 (2005-08-01), Keaveney et al.
patent: 6961400 (2005-11-01), Huff et al.

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