Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2000-05-17
2003-12-16
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S500000, C327S156000
Reexamination Certificate
active
06665809
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to system clocking in computer systems, particularly it relates to system clocking in connected network computer systems with an enhanced degree of performance and reliability. Even more particularly, it relates to a simplified method for correcting clock frequencies in order to adjust the clocks to an external reference time source.
BACKGROUND OF THE INVENTION
The present invention has a broad field of application, which includes any computer system which has a clock and any requirement to adjust said clock to any outer reference time source. Thus it can be applied in a large range of computer systems from a single stand-alone PC, or any computing device being even smaller than a PC to larger systems, in particular mainframe systems and even more particularly to a high-end system of inter-connected high-performance integrated system clusters in which each cluster comprises a plurality of central electronic complexes further referred to herein as CEC, i.e., some arrangement of high performance mainframe computer and its associated environment.
The present invention will be described with particular respect to such high-end systems for which the characterizing features of the invention are particularly well-suited, although its scope is as indicated above and should not be limited to high-end systems.
In high-end systems, the application work is distributed all over the plurality of CECs in multiple clusters. For achieving good performance the clusters are connected via high-speed optical fiber cables.
Especially in highly sophisticated applications running in such systems having a great need for system stability and reliability (like banking applications and the like), a proper operation of such a clustered application needs a precisely synchronized and reliably supplied time information in order to have the same time base everywhere in the plurality of clusters.
Such a system is described with its requirements concerning the time facility in IBM Journal Of Research and Development, Vol. 36, No. 4, July 1992, p. 658. Here is expressed that such a tough requirement of system availability implies that the possibility to maintain a plurality of ‘distributed’ time sources in each CEC, for example, is excluded. Thus, one central time information supplier is needed for the whole system.
As, however some degree of time supplier failure safety is required, at least two redundant time information suppliers, further exemplarily referred to herein as Sysplex Timers (ST) as they are called in IBM S/390 systems are required. Each ST is in turn connected with an external absolute time source further referred to as ETS, such as Global Positioning System (GPS) time source or the like. The two STs are connected with the system via particular, dedicated high speed cables. Such a type of system is depicted in
FIG. 1
where two clusters are depicted, each with a respective ST. To a given time only one of said time sources supplies the plurality of CECs with time information. Time information is synchronized between the two time sources with a dedicated time information line, again. On a failure in said ‘active’ time source the other, i.e., stand-by time source replaces the operation of the first.
As can be seen already from the figure a plurality of cables transmitting time information are required for maintaining such a prior art system. As a first disadvantage such arrangements of Sysplex Timers are very expensive. Also, the obligation to precisely synchronize the time information entering in each CEC has to be considered in order to provide exactly synchronized clock signals. With prior art techniques this can be achieved, but such solutions are complex and expensive. The synchronization aspect is more important given longer distances between a respective CEC and the central ST since the signal speed along some kilometers leads to transmission time delays which are not negligible compared to time periods of 10
−8
S in a clock cycle having a frequency of e.g. 100 Mhz. Another disadvantage of the prior art technique is that so many time information transmitting cables are required.
In order to overcome said disadvantages it would be desirable to integrate a timing functionality comparable to the conventional Sysplex Timing facility into the clock. chip of each CEC, (as e.g., the S/390 clock chip using IBM mainframe terminology), while having an accurately synchronized time base which is valid in all portions of the system independent from the geographic situation of any system portion.
With this ‘decentralizing’ approach, however, the plurality of decentralized clocks each residing on a CEC clock chip would have to be synchronized with the chosen common external time source. Moreover, the decentralized clocks would have to be corrected continuously and individually as any precision oscillator has only a limited accuracy which results in a clock operation which is either too slow or too fast compared to the external reference time source.
Such a correction and synchronizing task is solved in prior art only in a centralized approach using VCXOs as described above with reference to
FIG. 1
by expensive time correction circuits which use analogue and digital components.
The best results for integrating such a Sysplex timer functionality could be expected by using high precision temperature compensated crystal oscillate (TCXO) as timer clocks. As, additionally, the timer base supplied by this oscillator should, however, also be able to follow the frequency of already existing systems having a Sysplex Timer, a frequency variation, like it is possible with a VCXO (Voltage Controlled Cristal Oscillator) is required. The problem is that a VCXO is not stable enough if it can be pulled by 50 PPM. The stability error of such a VCXO would be about 20 PPM which is a factor of ten to high,
It is thus an object of the present invention, to overcome these difficulties and to provide in a simple and less expensive way a precisely synchronized clock information in multiple locations in a distributed system.
It is a further object of the present invention to provide such a method and system in which the clock is additionally able to follow a predetermined prior art external time reference (ETR) frequency, without suffering from e.g. the enormous expense of cabling for transporting the time information.
SUMMARY OF THE INVENTION
The foregoing and other objects of the invention are achieved by the features stated in enclosed independent claims. Further advantageous arrangements and embodiments of the invention are set forth in the respective subclaims. The basic idea comprised of the present invention into decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of time suppliers caused by said decentralization.
This is achieved by the general approach not to readjust the oscillator(s), but, instead, to accept the inaccuracy of the physical device ‘oscillator’ but to measure its inaccuracy and to correct it repeatedly with the aid of a continuous correction calculation procedure which is advantageously done in a digital way under usage of ETS input information and system oscillator output information.
In particular, this is achieved in a first basic approach of the inventive concepts by repeatedly modifying a piece of the used time signal in order to adjust the naturally inaccurate time signal, (i.e. clock signal, coming from the TCXO with the reference time source ETS). This is done in a circuit comprising a controller which is reading, i.e., measuring periodically the external reference time and the system time. Further, said circuit comprises a frequency multiplier PLL and a subsequent frequency divider which is normally operated with a ‘neutral’ divisor value in order to let the time signal unchanged and with preferably only two correction divisor values, of which one being responsible to
Goldrian Gottfried Andreas
Gregg Thomas Anthony
Dougherty Anne V.
Jennings Derek S.
Lee Thomas
Nieves Michael
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