Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-14
2004-09-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06792589
ABSTRACT:
BACKGROUND
This invention relates in general to digital circuits and, more specifically, to design of digital circuits that are laid-out with cells.
Mathematics is one attempt for humankind to understand the universe around them. As technological advancement occurs, mathematical concepts and algorithms grow to enable and/or support those advancements. Within the context of digital design, Boolean logic is the mathematical construct used to manipulate and optimize digital circuits. Nearly every electronic device today relies upon some type of Boolean logic for any embedded digital circuits. Other mathematical constructs, however, are possible that allow further optimization of digital designs. Changes to the processing of digital design are necessary when avoiding Boolean logic elements.
Today application specific integrated circuit (ASIC) are specified using netlists of library cells for a particular process of a foundry or fabrication facility. These netlists are used to fabricate integrated circuits made up of the library cells. A few hundred library cells are typically available for a particular process that include AND gates, OR gates, flip-flops (F/F), and buffers. When a new fabrication process is developed, engineers custom layout each of the library cells to get the most optimal performance from each cell.
REFERENCES:
patent: 4792909 (1988-12-01), Serlet
patent: 4849928 (1989-07-01), Hauck
patent: 5040139 (1991-08-01), Tran
patent: 5051917 (1991-09-01), Gould et al.
patent: 5128871 (1992-07-01), Schnitz
patent: 5162666 (1992-11-01), Tran
patent: 5200907 (1993-04-01), Tran
patent: 5225991 (1993-07-01), Dougherty
patent: 5349659 (1994-09-01), Do et al.
patent: 5461557 (1995-10-01), Tamagawa
patent: 5526276 (1996-06-01), Cox et al.
patent: 5548231 (1996-08-01), Tran
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5649165 (1997-07-01), Jain et al.
patent: 5712806 (1998-01-01), Hennenhoefer et al.
patent: 5780883 (1998-07-01), Tran et al.
patent: 5796128 (1998-08-01), Tran et al.
patent: 5801551 (1998-09-01), Lin
patent: 5805462 (1998-09-01), Poirot et al.
patent: 5859547 (1999-01-01), Tran et al.
patent: 5894227 (1999-04-01), Acuff
patent: 5953519 (1999-09-01), Fura
patent: 5987086 (1999-11-01), Raman et al.
patent: 6051031 (2000-04-01), Shubat et al.
patent: 6173435 (2001-01-01), Dupenloup
patent: 6184718 (2001-02-01), Tran et al.
patent: 6185719 (2001-02-01), Sako
patent: 6205572 (2001-03-01), Dupenloup
patent: 6263483 (2001-07-01), Dupenloup
patent: 6275973 (2001-08-01), Wein
patent: 6282695 (2001-08-01), Reddy et al.
patent: 6288593 (2001-09-01), Tran et al.
patent: 6289491 (2001-09-01), Dupenloup
patent: 6289498 (2001-09-01), Dupenloup
patent: 6292931 (2001-09-01), Dupenloup
patent: 6295636 (2001-09-01), Dupenloup
patent: 6313666 (2001-11-01), Yamashita et al.
patent: 6356112 (2002-03-01), Tran et al.
patent: 6359468 (2002-03-01), Park et al.
patent: 6367065 (2002-04-01), Leight et al.
patent: 6467074 (2002-10-01), Katsioulas et al.
patent: 2002/0069396 (2002-06-01), Bhattacharya et al.
patent: 2002/0087939 (2002-07-01), Greidinger et al.
patent: WO 02/103757 (2002-12-01), None
Balajee, S. et al., “Automated AC (timing) characterization for digital circuit testing”, VLSI Design, 1998. Eleventh International Conference on , Jan. 4-7, 1998 pp.: 374-377.*
Patel, D., “CHARMS: characterization and modeling system for accurate delay prediction of ASIC designs”, Custom integrated Circuits Conference, 1990., Proceedings of the IEEE 1990, May 13-16, 1990 pp.: 9.5/1-9.5/6.*
Leung, S.C. et al., “A syntax-directed translation for the synthesis of delay-insensitive circuits”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.: 2, Issue: 2 , Jun. 1994 pp.: 196-210.*
Rollins, J.G., “Numerical simulator for superconducting integrated circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.: 10, Issue: 2 , Feb. 1991 pp.: 245-251.*
Devadas, S. Optimal Layout Via Boolean Satisfiablility, 1989 IEEE International Conference on Computer-Aided Design Nov. 5, 1989, pp. 294-297.
Falkowski, B.J. et al., Efficient Algorithms For the Calculation of Arithmetic Spectrum from OBDD and Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions 1994 IEEE International Symposium on Circuits and Systems, May 30, 1994, vol. 1, pp. 197-200.
Method for Identifying Technology Primitive in Logic IBM Technical Disclosure Bulletin, May 1992 Vo. 34, No. 12, pp. 359-361.
Upton, M. et al. Integrated Placement for Mixed Macro Cell and Standard Cell Designs Proceedings of 27th ACM/IEEE Design Automation Conference, Jun. 24, 1990, pp. 32-35.
Fletcher, William I.,An Engineering Approach to Digital Design, MSI and LSI Circuits and Their Applications, 1980, Prentice-Hall, Inc., Englewood Cliffs, NJ, pp. 210-226.
Yano, Kazuo, et al., “Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs,” IEEE 1994 Custom Integrated Circuits Conference, pp. 603-606.
Cameron Eric G.
Miles Lowell H.
Whitaker Sterling R.
Levin Naum B
Science & Technology Corporation @ UNM
Siek Vuthe
LandOfFree
Digital design using selection operations does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital design using selection operations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital design using selection operations will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3274240