Digital delay phase locked loop

Details Digital delay phase locked loop Digital delay phase locked loop

2000-12-11

2003-04-22

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S161000

Reexamination Certificate

active

06553088

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89221041, filed Dec. 4, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a delay phase locked loop. More particularly, the invention relates to a digital delay phase locked loop using binary control to achieve a fast phase lock effect.
2. Description of the Related Art
FIG. 1
shows a circuit diagram of a conventional digital delay phase locked loop. A clock signal CLK is input to a buffer
10
which is constructed by several unit delays (UD) to perform a delay operation. The clock signal is then sent to a buffer
12
, and a phase locked clock signal DCLK is output thereby. A phase comparator
14
is also included to compare the input clock signal CLK and the phase locked signal DCLK. A comparison signal according to the difference in periods of these two signals CLK and DCLK is generated and output. For example, as shown in
FIG. 1
, either of the UP and DOWN is used to perform an advance or delay modification of the difference to achieve the objective of phase lock.
FIGS. 2 and 3
show the waveforms of the above signals. In
FIG. 2
, the difference in periods between the clock signal CLK and the phase locked signal DCLK is Td. The comparison signal UP output by the phase comparator
14
as shown in
FIG. 1
gradually decreases the period difference Td between the signals DCLK and CLK under the influence of the delay apparatus
10
. As shown in
FIG. 2
, period difference Td is gradually decreased to Td−(1*Tud), Td−(2*Tud) and Td−(3*Tud).
Similarly, from the comparison signal DOWN output by the phase comparator
14
, it is clear that Td is far larger than one cycle, and the rising point of the phase locked signal DCLK is located at a low voltage of the clock signal CLK. Therefore, the phase comparator
14
outputs the comparison signal DOWN to have the signal DCLK reduce from Td to Tm+(1*Tud), Td+(2*Tud) and Td+(3*Tud) to reduce the period difference.
In the above delay apparatus, shift registers are used as the controller for the unit delays. Only one unit is shifted once. When the Td is large, a very long time is required to complete the phase lock. When the bandwidth becomes magnificent, the number of unit delays has to be increased. It is thus difficult to meet the current requirements in industry.
SUMMARY OF THE INVENTION
The invention provides a digital delay phase locked loop. A phase comparing converter is designed to convert the time differenct between a phase locked data signal and an input data signal to a digital output comparison signal. The comparison signal is sent to an adder-register with multiple bits. Using a demultiplexer, the delay function of the delay apparatus is controlled to quickly perform the phase lock.
The digital delay phase locked is applicable to receive an input clock signal. After a fast phase lock, a phase locked clock signal is output. The above digital delay phase locked loop comprises a delay apparatus, a buffer, a phase comparing converter, an adder-register, a clock divider and a demultiplexer.
The delay apparatus performs a delay function while receives an input clock signal, and then outputs a delay data signal. After receiving the delay clock signal, the buffer outputs a phase locked signal. The time difference of the phase locked data signal is comapred to that of the input data signal, a comparison signal converted into digits is then output. The adder-register receives and temporary stores the comparison signal. After receiving the clock signal, the clock divider outputs a data refresh signal to the adder-register. A modified signal is then output by the adder-register. The modified signal is received by the demultiplexer, and a control signal is output from the demultiplexer to the delay apparatus to control the delay function, so as to achieve the phase lock function.
The above delay apparatus comprises several unit delays connected to each other in series. The demultiplexer comprises several control gates connected in parallel. Each control gate is corresponding to one unit delay. The control gate comprises and an AND gate or an NAND. The adder-register comprises a multiple bit register to control the generation of several unit delays at once, so as to achieve the fast phase lock effect.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 6087868 (2000-07-01), Millar
patent: 6150859 (2000-11-01), Park
patent: 6359482 (2002-03-01), Miller, Jr. et al.

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