Digital delay lock loop for setup and hold time enhancement

Details Digital delay lock loop for setup and hold time enhancement Digital delay lock loop for setup and hold time enhancement

2006-10-31

2006-10-31

Chin, Stephen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S377000, C714S770000

Reexamination Certificate

active

07130367

ABSTRACT:
A digital delay lock loop (DLL) circuit for receiving parallel data and clock signals, deserializing the high speed parallel data to low speed data, and for improving setup and hold times. A DLL circuit for an N-bit datapath, includes a clock DLL configured to provide a clock signal pulse within an eye opening of each of N data signals. The DLL circuit further includes N data DLLs, each being configured to adjust a delay of a data signal to substantially center the eye opening of the data signal on the clock signal pulse.

REFERENCES:
patent: 5987085 (1999-11-01), Anderson
patent: 6370200 (2002-04-01), Takahashi
patent: 6426984 (2002-07-01), Perino et al.
patent: 2003/0006877 (2003-01-01), Anand
patent: 2003/0046618 (2003-03-01), Collins
Lee, Thomas H., et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,” IEEE J. Solid-State Circuits, vol. 29, No. 12, Dec. 1994.

Affiliated with

Also associated with

Rating

Digital delay lock loop for setup and hold time enhancement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital delay lock loop for setup and hold time enhancement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital delay lock loop for setup and hold time enhancement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3616106