Digital delay lock loop for clock signal frequency multiplicatio

Details Digital delay lock loop for clock signal frequency multiplicatio Digital delay lock loop for clock signal frequency multiplicatio

1997-01-07

1998-06-23

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 375374, 375377, 327158, 327160, H03D 324

Patent

active

057712646

ABSTRACT:
A digital delay lock loop for generating frequency multiples of an input clock signal includes a programmable digital oscillator, a phase comparator, a programmable counter and delay control logic. The programmable digital oscillator is a ring connected programmable delay line and inverter which together generate an output clock signal having a frequency which depends upon the time delay of the programmable delay line. The phase comparator compares the phase of the output clock signal to that of a reference clock signal and generates a phase error signal which represents the phase difference between such signals. The programmable counter, programmed and reprogrammed with the arrival of every reference clock signal pulse, counts the output clock signal pulses to generate a count signal. The delay control logic, in response to the phase error signal and count signal, programs the time delay of the programmable delay line, thereby causing the output clock signal frequency to be the desired multiple of the reference clock frequency.

REFERENCES:
patent: 3961282 (1976-06-01), Chen et al.
patent: 4309673 (1982-01-01), Norberg et al.
patent: 4338569 (1982-07-01), Petrich
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4677318 (1987-06-01), Veenstra
patent: 4689581 (1987-08-01), Talbot
patent: 4713792 (1987-12-01), Hartman et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 5121006 (1992-06-01), Pedersen
patent: 5241224 (1993-08-01), Pedersen et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5350954 (1994-09-01), Patel
patent: 5420592 (1995-05-01), Johnson
patent: 5488641 (1996-01-01), Ozkan
patent: B14617479 (1993-09-01), Hartmann et al.
Dr. Dao-Long Chen, "Designing on-Chip Clock Generators", Circuits and Devices, Jul. 1992, pp. 32-36.
Mark G. Johnson and Edwin L. Hudson, "A Variable Delay Line PLL for CPU-Coprocessor Synchronization", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1218-1223.
Ian A. Young, Jeffrey K. Greason and Keng L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
Uming Ko, Shannon A. Wichman, Shawn Castrianni, "A 30-ps Jitter, 3.6-.mu.s Locking 3.3-Volt Digital PLL for CMOS Gate Arrays", IEEE 1993 Custom Integrated Circuits Conference, pp. 23.3.1-23.3.4.
Florence Lee, "PLL Application Note", LSI Logic Corporation, Nov. 8, 1991, pp. 0-28.

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