Digital delay line

Details Digital delay line Digital delay line

1984-08-21

1986-09-09

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Signals

364900, 381 63, 328155, G11C 700

Patent

active

046113002

ABSTRACT:
A digital delay system employs a phase-locked loop to control a recall address generator. The phase-locked loop comprises a subtractor for determining the difference between the store address and the recall address and for producing a phase signal corresponding to this difference. The phase signal is directed to a voltage controlled oscillator for controlling the rate at which the recall address generator recalls data from a memory. A delay length is introduced as a phase error into the phase-locked loop. Input data is stored in a memory at a fixed rate, and recalled from the memory at a rate determined by the phase-locked loop. When the error signal is zero, the recall address rate will equal the store address rate and the respective addresses will be equal. When an error signal is introduced into the loop, the VCO will cause the recall address to advance or retard to produce the desired delay, and after the delay has been produced, the phase-locked loop will ensure that the recall address rate is equal to the store address rate. The phase error may be either a constant signal or a low-frequency signal.

REFERENCES:
patent: 4181975 (1980-01-01), Jenkins
patent: 4318183 (1982-03-01), Byington et al.

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