Digital data multiplying circuit

Details Digital data multiplying circuit Digital data multiplying circuit

1994-02-14

1996-02-06

Envall, Jr., Roy N.

Boots, shoes, and leggings

364760, G06F 752

Patent

active

054901014

ABSTRACT:
A digital data multiplying circuit has a double clock alternating sampler for alternately sampling the digital data applied from a plurality of input buses by a time-division system in accordance with a first system clock, a dual coefficient alternating multiplier for alternately multiplying digital data of each bus sampled by the double clock alternate sample with the multiplying coefficient corresponding to the digital data according to a first system clock and first and second primary clocks, and a data restorer for dividing the synchronized product data of the dual coefficient alternating multiplier into input data units according to the first system clock, a second system clock and the second primary clock and for outputting the result on a plurality of output buses. As a result, the digital data input to a plurality of input buses can be multiplied by a single multiplier.

REFERENCES:
patent: 4796216 (1989-01-01), Renner et al.
patent: 5166895 (1992-11-01), Makino
patent: 5262975 (1993-11-01), Ohki

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