Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-02-06
2004-02-03
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S097000, C326S098000, C326S052000, C326S054000, C326S055000
Reexamination Certificate
active
06686776
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a digital data coincidence determining circuit, and, more particularly, to a coincidence determining circuit which determines whether plural pieces of digital data coincide with one another by comparing the digital data bit by bit.
There is an address comparator for a memory circuit, which determines whether two pieces of digital data coincide with each other by comparing the two pieces of digital data bit by bit.
FIG. 1
is a schematic circuit diagram of a conventional coincidence determining circuit
100
. The coincidence determining circuit
100
determines whether two pieces of digital data A and B each consisting of n bits coincide with each other. The digital data A consists of bits A
0
, A
1
, . . . , A
n−1
and the digital data B consists of bits B
0
, B
1
, . . . , B
n−1
. The complementary values of the individual bits of the digital data A are /A
0
, /A
1
, . . . , /A
n−1
and the complementary values of the individual bits of the digital data B are /B
0
, /B
1
, . . . , /B
n−1
. The coincidence determining circuit
100
includes exclusive OR circuits XOR
0
, XOR
1
, . . . , XOR
n−1
for determining whether the digital data A and B coincide with each other by comparing the digital data A and B bit by bit. Each of the exclusive OR circuits XOR
0
, XOR
1
, . . . , XOR
n−1
generates a signal of a logical level “L” (Low) when the associated two bits coincide with each other, and generates a signal of a logical level “H” (High) when there is no coincidence.
The output signals of the exclusive OR circuits XOR
0
, XOR
1
, . . . , XOR
n−1
are applied to the gates of n-channel transistors TNS′
0
, TNS′
1
, . . . , TNS′
n−1
. Each transistor is connected between a wiring
110
, which is precharged to a high potential in a given clock cycle, and the ground. In case where at least one of the bits of the digital data A does not coincide with the associated bit of the digital data B, that transistor which is connected to the associated exclusive OR circuit is turned on, thus electrically connecting the wiring
110
to the ground. In case where all of the bits of the digital data A coincide with the associated bits of the digital data B, all of the transistors are turned off, thus electrically disconnecting the wiring
110
from the ground.
The coincidence
on-coincidence determining operation of the coincidence determining circuit
100
is performed as follows.
First, when a clock signal CLK
1
has a logical level “L”, the wiring
110
is precharged to a supply voltage VDD, supplying data to the individual exclusive OR circuits XOR
0
, XOR
1
, . . . , XOR
n−1
. When the clock signal CLK
1
rises to a logical level “H” thereafter, the wiring
110
is electrically disconnected from the power supply. When the digital data A and B coincide with each other, the wiring
110
becomes a high-impedance state and the potential of the wiring
110
is held at nearly the logical level “H”. When the digital data A and B do not coincide with each other, on the other hand, the wiring
110
is electrically connected to the ground, so that the potential of the wiring
110
is pulled down to the logical level “L”.
A change in the potential of the wiring according to the coincidence or non-coincidence of the digital data A and B is read through an AND circuit
111
. The AND circuit
111
outputs a logical product of a clock signal CLK
2
and the potential of the wiring. The clock signal CLK
2
rises with a delay from the rising of the clock signal CLK
1
. The AND circuit
111
generates a signal of a logical level “H” when the digital data A and B coincide with each other and generates a signal of a logical level “L” when they do not coincide with each other.
In this manner, the coincidence determining circuit
100
determines whether two pieces of digital data coincide with each other. In the present specification, a high potential (the supply voltage VDD or VDD−Vt (threshold value of a transistor)) is defined as the logical level “H” and a low potential (the ground potential VSS or VSS+Vt) is defined as the logical level “L”.
The circuit area of the coincidence determining circuit
100
increases as the number of bits of digital data increases. That is, every time the number of bits of digital data increases by one, an exclusive OR circuit XOR and an n-channel transistor should be additionally provided. It is therefore necessary to provide additionally nine transistors for an increase of one bit. In case of determining if three or more pieces of digital data coincide with one other, the circuit area of the coincidence determining circuit likewise increases with an increase in the number of pieces of digital data.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a digital data coincidence determining circuit which suppresses an increase in circuit area.
In a first aspect of the invention, there is provided a coincidence determining circuit for determining whether plural pieces of digital data, which includes first digital data and second digital data each consisting of a plurality of bits, coincide with one another. The coincidence determining circuit includes a wiring and a plurality of bit comparison circuits connected to the wiring and corresponding in number to the plurality of bits. Each bit comparison circuit includes first and second transistors connected in series between the wiring and a power supply line and third and fourth transistors connected in series between the wiring and the power supply line. The first transistor has a first control terminal to which a first logical signal of an associated bit of the first digital data is applied. The second transistor has a second control terminal to which an inverted signal of a second logical signal of an associated bit of the second digital data is applied. The third transistor has a third control terminal to which an inverted signal of the first logical signal is applied. The fourth transistor has a fourth control terminal to which the second logical signal is applied. The first to fourth transistors change a potential of the wiring by controlling conduction between the wiring and the power supply line and it is determined based on a change in the potential whether the plural pieces of digital data coincide with one another.
In a second aspect of the invention, there is provided a coincidence determining circuit for determining whether plural pieces of digital data, which includes first digital data and second digital data each consisting of a plurality of bits, coincide with one another. The coincidence determining circuit includes a wiring, a plurality of switching transistors connected in parallel between the wiring and a power supply line and corresponding in number to the plurality of bits, and a plurality of bit comparison circuits respectively connected to switching control terminals of the plurality of switching transistors. Each bit comparison circuit includes a first transistor having a first input/output terminal connected to the switching control terminal of an associated one of the switching transistors, a second input/output terminal and a first control terminal, and a second transistor having a third input/output terminal connected to the switching control terminal of an associated one of the switching transistors, a fourth input/output terminal and a second control terminal. A first logical signal of an associated bit of the first digital data, an inverted signal of the first logical signal, a second logical signal of an associated bit of the second digital data and an inverted signal of the second logical signal are respectively applied to the second and fourth input/output terminals and the first and second control terminals such that the associated switching transistor is turned off only when the associated bit of the first digital data coincides with the associated bit of the second digital data. As conduction of the plurality of switch
Saitoh Hirofumi
Sakata Kohji
Sanyo Electric Co,. Ltd.
Tran Anh
Westerman Hattori Daniels & Adrian LLP
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