Digital configurable macro architecture

Details Digital configurable macro architecture Digital configurable macro architecture

2001-07-18

2003-01-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S040000, C326S037000, C326S041000, C326S039000

Reexamination Certificate

active

06507214

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to programmable digital circuits. More particularly, the present invention relates to the field of programmable digital circuits which are dynamically configurable to any one of various digital functions by changing the contents of configuration registers.
2. Related Art
Microcontrollers or controllers have been utilized in various applications for many years. Primarily, microcontrollers are used in control-oriented applications that are interrupt-driven, sensing and controlling external events. Microcontrollers are frequently found in: appliances (e.g., microwave oven, refrigerator, television, VCR, stereo), computers and computer equipment (e.g., laser printers, modems, disk drives), automobiles (e.g., engine control, diagnostics, climate control), environmental control (e.g., greenhouse, factory, home), aerospace, and thousands of other uses.
The Field Programmable Gate Array (FPGA) has become very popular in recent years, even being utilized in several microcontroller applications. One reason for its popularity is the shortage in design cycle time that may be achieved by using programmable devices. Typically, FPGAs offer the highest logic capacity. FPGAs can be programmed to realize different digital functions. In particular, many FPGAs have programmable look-up tables to realize different digital functions. Typically, a FPGA contains from a few to tens of thousands of programmable logic blocks and an even greater number of flip-flops, each programmable logic block having a look-up table, multiplexors, and flip-flops. Most FPGAs do not provide 100% interconnect between programmable logic blocks.
However, FPGAs are highly inefficient with respect to chip area, increasing their cost. Typically, less than half of the logic resources in the FPGA are used to realize a digital function. Moreover, FPGAs need to have their look-up tables re-programmed in order to enable them to implement a new digital function, which is a time consuming task.
FPGAs are not ideally suited for microcontroller applications. Microcontroller applications are very cost-sensitive. A FPGA is not able to realize the number of digital functions that are demanded by today's microcontroller applications within these strict cost constraints.
SUMMARY OF THE INVENTION
A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block. The programmable digital circuit blocks can be configured, for example, as timers, counters, serial communication ports, cyclic redundancy generators/checkers (CRC), or pseudo random sequence generators (PRS). The user selects the digital function that is needed and configures the programmable digital circuit block accordingly.
The programmable digital circuit blocks can be configured to coupled in series or in parallel to handle more complex digital functions. For example, a 24-bit timer can be designed by coupling three 8-bit programmable digital circuit blocks that have been individually configured as 8-bit timers. Additionally, a first programmable digital circuit block that is configured as a CRC generator can feed a second programmable digital circuit block that is configured as a serial output communication port.
More importantly, the configuration of the programmable digital circuit block is determined by its small number of configuration registers. This provides much flexibility. In particular, the configuration of the programmable digital circuit block is fast and easy since changes in configuration are accomplished by changing the contents of the configuration registers, whereas the contents are generally a small number of configuration data bits. Thus, the programmable digital circuit block is dynamically configurable from one predetermined digital function to another predetermined digital function for real-time processing.
These and other advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.


REFERENCES:
patent: 5880598 (1999-03-01), Duong
patent: 6304101 (2001-10-01), Nishihara

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