Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-03-30
2002-03-05
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C340S146200, C708S671000
Reexamination Certificate
active
06353646
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of digital comparators, and more specifically to a digital comparator using a carry lookahead adder.
2. Discussion of the Related Art
Many electronic circuits use numerical calculation circuits enabling in particular to compare two numbers A and B having the same number of bits.
FIG. 1
very schematically shows the structure of a conventional complete comparator, providing an indication of equality, superiority A>B, or inferiority A<B.
A first block
11
receives on a first input an operand A, on a second input an operand B, and generates an output signal indicating whether A=B. A second block
12
receives on two inputs operands A and B, performs operation A−B and generates two outputs, one corresponding to A<B, and the other corresponding to A≧B. Logic elements
13
,
14
receiving the signals corresponding to A≧B and A=B determine whether A=B or whether A>B. With operation A−B corresponding, in binary coding, to operation A+{overscore (B)}+1, block
11
is conventionally an adder adding A, {overscore (B)}, and an incoming carry equal to 1.
In the following description, A
i
and B
i
will designate the n bits of operands A and B, i being included between 1 and n.
FIG. 2
shows an example of structure of block
11
of FIG.
1
. An X-OR gate
21
receives on a first input bit A
1
of the first operand A and on a second input bit B
1
of the second operand B. The output of X-OR gate
21
will be at a high logic level “1” in case of an equality between bits A
1
and B
1
·n X-OR gates
21
thus enable determining, rank by rank, the equality or the inequality of the bits of same rank of the first and second operands. The outputs of these X-OR gates are connected to the n inputs of an AND gate
22
. The output of AND gate
22
will be at a high logic level “1” in case of a bit to bit equality of the first and second operands.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a complete comparator using a reduced number of logic gates.
This objects as well as others is achieved by a digital comparator which includes a first block receiving on first inputs the bits of a first operand A of n bits and on second inputs the logic complements of the bits of a second operand B of n bits, generating a propagation signal
p
n
=
π
i
=
1
n
P
i
where
P
i
=
A
i
+
B
_
i
,
and a generation signal
g
n
=
∑
i
=
1
n
-
1
(
G
i
π
j
=
i
+
1
n
P
j
)
+
G
n
where
G
i
=
A
i
·
B
_
i
,
g
1
=
G
1
,
which includes a second block receiving on a first input the most significant bit A
n
of the first operand, on a second input the logic complement {overscore (B)}
n
of the most significant bit B
n
of the second operand, on a third input propagation signal P
n
, on a fourth input generation signal g
n
, generating signals C
n
and S
n+1
such that C
n
=p
n
+g
n
and S
n+1
=(p
n
+g
n
)⊕A
n
⊕{overscore (B)}
n
, where sign ⊕ represents operation X-OR, and which also includes a third block receiving on a first input signal p
n
and on a second input signal g
n
, and generating a signal E such that E=p
n
·{overscore (g)}
n
, indicating by a predetermined state that operands A and B are equal.
According to another aspect of the present invention, the first and second blocks both belong to a carry lookahead adder, the first block belonging to a block of the adder used to calculate all propagation signals p
i
and all generation signals g
i
, where i is included between 1 and n, and the second block belonging to a block of the adder used to calculate all sum signals S
i
, where i is included between 1 and n+1, and outgoing carry signal C
n
, an incoming carry signal of the second block being set to 1.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 4450432 (1984-05-01), Schmidtpott et al.
patent: 4760374 (1988-07-01), Moller
patent: 5146592 (1992-09-01), Pfeiffer et al.
patent: 5260680 (1993-11-01), Glass
patent: A-38 25 388 (1990-02-01), None
French Search Report from French Patent Application 98/04205, filed Mar. 31, 1998.
Patent Abstracts of Japan, vol. 014, No. 226 (P-1047), May 14, 1990 & JP-A-02 054333 (Mitsubishi Electric Corp.).
Morris James H.
STMicroelectronics S.A.
Vo Don N.
Wolf Greenfield & Sacks P.C.
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