Television – Image signal processing circuitry specific to television – Chrominance signal demodulator
Reexamination Certificate
2000-09-11
2003-03-25
Miller, John (Department: 2614)
Television
Image signal processing circuitry specific to television
Chrominance signal demodulator
C348S505000, C348S506000, C348S508000
Reexamination Certificate
active
06538702
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a digital color signal reproducing circuit for a television receiver capable of receiving television broadcasting based on a different televisions systems, and more particularly to a technique for realizing a color signal reproducing circuit with a simple structure while using the digital color signal reproducing circuit commonly in different televisions systems and for achieving YC separation and demodulation of color signal with a high degree of precision without changing its clock frequency considerably.
BACKGROUND OF THE INVENTION
In recent years, as television receivers come into wide use around world, receiver of different television systems is demanded to be used commonly and higher in performance. For example, a digital color signal reproducing circuit is demanded to be used commonly in the NTSC and PAL systems and higher in performance.
An example of a conventional digital color signal reproducing circuit is described below with reference to FIG.
3
.
FIG. 3
shows a block diagram of the digital color signal reproducing circuit disclosed in Japanese Laid-open Patent H11-8857.
In
FIG. 3
, clock generator
1101
generates clock pulse
1102
at a frequency of an integral multiple (e.g. 4 times: 27 MHz) of the sampling frequency of color-difference signal, 6.75 MHz. In response to clock pulse
1102
, A/D converter
1104
samples analog chrominance subcarrier signal fed from input terminal
1103
and converts it into 8-bit digital data.
First demodulator
1105
multiplies the output from A/D converter
1104
by the output from sine wave generator
1112
at every clock pulse
1102
and thereafter eliminates high frequency components for thinning-out processing. Then, it outputs 6.75-MHz color-difference signal (B-Y signal) from output terminal
1107
.
Second demodulator
1106
multiplies the output from A/D converter
1104
by the output from cosine wave generator
1113
at every clock pulse
102
and thereafter eliminates high frequency components for thinning-out processing. Then, it outputs 6.75-MHz color-difference signal (R-Y signal) from output terminal
1108
.
NTSC phase compensator
1202
performs mean value processing on color burst (hereinafter abbreviated as “burst”) period of output signals from demodulator
1105
and
1106
. Then, it detects and outputs the phase differences between reference subcarrier signal and burst signal. PAL phase compensator
1203
performs mean value processing on burst period of output signals from demodulator
1105
and
1106
. Then, it detects and outputs the phase difference between reference subcarrier signal and burst signal.
Selector
1204
selects the output from either phase compensator
1202
or
1203
in accordance with NTCS/PAL switching signal.
Phase generator
1110
constitutes a voltage control oscillator (VCO) that changes phase lead quantities per clock pulse. The VCO is controlled by the phase difference supplied from phase compensator
1202
or
1203
, and outputs a phase lead quantity per clock pulse.
Rounding circuit
1111
omits the least significant bit of the output from phase generator
1110
to reduce the number of bits (rounding operation) and outputs 10-bit phase information.
Sine wave generator
1112
and cosine wave generator
1113
are composed of a ROM that stores data corresponding to one wavelength of sine wave and one wavelength of cosine wave. Ten-bit data from rounding circuit
1111
is fed into the address line of the ROM. The ROM outputs sine and cosine components of 8-bit reference subcarrier signal to first and second demodulator
1105
and
1106
at every clock cycle.
During the NTSC operation, demodulator
1105
and
1106
, phase compensator
1202
, selector
1204
, phase generator
1110
, rounding circuit
1111
, sine wave generator
1112
, and cosine wave generator
1113
form a loop circuit. This loop circuit operates as an NTSC automatic phase control (hereinafter abbreviated as APC) circuit and always generates reference subcarrier conforming to the normal demodulation axis.
During the PAL operation, demodulator
1105
and
1106
, phase compensator
1203
, selector
1204
, phase generator
1110
, rounding circuit
1111
, sine wave generator
1112
, and cosine wave generator
1113
form a loop circuit. This loop circuit operates as a PAL APC circuit and always generates reference subcarrier conforming to the normal demodulation axis.
As a result, analog chrominance subcarrier signal is demodulated so as to conform to the normal demodulation axes in first and second demodulator
1105
and
1106
and supplied to output terminals
1107
and
1108
as R-Y and B-Y signals.
The above structure is a digital color signal reproducing circuit that converts analog chrominance subcarrier signal into digital signal and thereafter demodulates into color-difference signals. Meanwhile, recent advances in digital technologies have realized a digital color signal reproducing circuit that separates chrominance subcarrier signal from digital composite signal converted from analog composite signal and thereafter demodulates into color-difference signals. Moreover, in this method, reduction of cross-color and dot crawl interference is desired.
However, when color-difference signals are demodulated from digital chrominance subcarrier signal, i.e. the output from the YC separator, using the conventional color signal reproducing circuit, there are the following problems.
Since the clock pulse do not lock to the burst signal and horizontal synchronizing signal of composite signal, three-dimensional YC separation is not performed accurately and thus some interference remains.
In sophisticated three-dimensional YC separation for the NTSC system, high line correlation and frame correlation in chrominance components are utilized. For this reason, inter-frame and inter-line signals can accurately be added or subtracted, only when clock pulse lock to the burst signal and have a frequency equal to an integral multiple of that of burst signal.
In addition, in the PAL system, the use of clock pulse locking to burst signal facilitates YC separation using line memory.
In the conventional example, when the clock frequency is selected as an integral multiple of the chrominance subcarrier frequency in order to allow the clock pulse to lock to the burst signal, clock frequencies differ considerably with systems. For example, with the PAL system, the clock frequency is 4.43 MHz×4=17.72 MHz; and with the NTSC system, the clock frequency is 3.58 MHz×4=14.32 MHz.
FIG. 6
shows a block diagram of a recursive digital filter. Such a recursive digital filter is used for a low-pass filter, YC separator, sync separator and other circuits in a color signal reproducing circuit. In
FIG. 6
, the recursive digital filter is composed of adder
601
, delay circuit
602
that delays input signal by n clock pluses, and gain controller
603
that controls the amplitude of input signal and outputs the controlled signal.
When the clock frequency is changed in accordance with the systems, the characteristic of the recursive digital filter change with the clock frequency, so gain coefficient of gain controller
603
must be changed in accordance with the systems. This poses a problem that more complicated circuit is necessitated. To solve the problem, circuit that allows the clock frequency to be set to an any multiple of the chrominance subcarrier frequency is desired.
SUMMARY OF THE INVENTION
To solve the problem, a digital color signal reproducing circuit of the present invention has:
an A/D converter that samples analog composite signal using a sampling clock and converts them into digital composite signal;
a YC separator that separates luminance signals and chrominance subcarrier signal from the digital composite signal and outputs respective signals;
a gain controller that controls the amplitude of the chrominance subcarrier signal and outputs the controlled signal;
a first multiplier that multiplies output signal of the gain controller by sine component of refere
Ando Hiroshi
Moribe Hiroshi
Morita Hisao
Shibutani Ryuichi
Taketani Nobuo
McDermott & Will & Emery
Miller John
Tran Trang U.
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