Digital CMOS-input with N-channel extended drain transistor...

Electronic digital logic circuitry – Reliability – Fail-safe

Reexamination Certificate

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C326S083000

Reexamination Certificate

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11231673

ABSTRACT:
A circuit and a method are given, to realize an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range for operating standard CMOS devices and a high-voltage range exceeding said standard CMOS low-voltage operating range significantly by multiples and thus necessarily utilizing input ports with an intrinsic high-voltage protection feature. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with standard modern integrated circuit technologies in CMOS technology.

REFERENCES:
patent: 6169432 (2001-01-01), Sharpe-Geisler
patent: 6181193 (2001-01-01), Coughlin, Jr.
patent: 6320408 (2001-11-01), Kwong
patent: 6441670 (2002-08-01), Coughlin et al.
patent: 6452440 (2002-09-01), Rapp
patent: 6781415 (2004-08-01), Clark et al.
patent: 6856168 (2005-02-01), Oertle et al.
patent: 2006/0103427 (2006-05-01), Bhattacharya et al.
An Internal Technical Report by Rainer Krenzke et al., of Oct. 2004, “A 36-V H-Bridge Driver Interface in a Standard 0.35-μm CMOS Process”.

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