Digital clock with controllable phase skew

Details Digital clock with controllable phase skew Digital clock with controllable phase skew

2000-03-31

2001-11-13

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S236000, C327S241000, C327S166000, C327S160000

Reexamination Certificate

active

06316982

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to clock circuits, and more particularly relates to digital clocks having phase control of the clock output. The invention has application, for example, to wireless communications systems.
BACKGROUND OF THE INVENTION
Many circuits require one or more clock signals for their operation. Such clock signals are typically provided by clock generator circuits, or, simply, clock circuits, that are driven by a reference clock signal that is provided from a source external to the clock circuit.
It is desirable to synthesize a clock circuit from circuitry comprised common digital circuits found in a typical VLSI standard cell library. Such common digital circuits include NAND gates, NOR gates, and FLIP-FLOPS. In this way, a clock generation circuit can be manufactured efficiently with respect to reliability and cost. On the other hand, common clock circuit techniques involve the use of PLL's and frequency dividers. However, PLL's and dividers are usually comprised of special analog components. For example, even a digital phase lock loop requires a special analog circuit known as a phase detector. Furthermore, it is often required to accompany a digital phase lock loop with external analog components such as capacitors.
Digital clocks are clock circuits implemented entirely in digital circuitry, and thus avoid the aforementioned problems. It is desired to provide a digital clock having the capability of deriving an output clock signal from a reference clock signal, where the output clock signal is a rational number multiple of the reference clock. In other words, given a reference clock provided at a frequency f
R
, the present invention provides an output clock having a frequency f
O
, such that
f
0
=
M
N
⁢
f
R
,
wherein M and N are integers, and M<N.
For example, in a code division multiple access (“CDMA”) receiver unit, a reference clock may be provided at a frequency, f
R
, of 19.2 MHz, while it is desired to provide an system clock for the receiver system at a frequency, f
O
, of 9.8304 MHz. A frequency of 9.8304 MHz is equal to 19.2 MHz multiplied by 64/125. In other words, in this case, M is 64 and N is 125.
Now, a divide-by-two situation would be presented in this case if N were 128. However, such is not the case, and so a simple divide-by-two clock divider circuit is not available to provide this system clock.
Further, in CDMA applications, for example, it would be advantageous to provide a clock generator having the above-described capability, wherein the clock generator is also continuously controllable. In such applications, the circuits driven by the clock generator are attempting to track individual signals of multiple path signals arriving at the receiver. Each such signal may itself be changing in phase, for example as the receiver unit moves around in the vicinity of a base station. It would be useful to be able to change the frequency of the clock driving these circuits, to aid in the tracking process. And, it would be desirable to effect this control in a way that is easily accessible to software running on a system in which the circuits are utilized.
Accordingly, it is desired to provide a digital clock generator that permits the generation of an output clock from a reference clock, wherein the output clock is a rational number multiple of the reference clock. Further, it is desired to provide such a digital clock generator having programmable control over the rational number multiplier. The present invention provides such a clock generator.
SUMMARY OF THE INVENTION
In accordance with the present invention there is provided a method and apparatus for generating an output clock signal having a frequency f
O
derived from a reference clock signal having a frequency f
R
, such that
f
0
=
M
N
⁢
f
R
,
is satisfied, wherein M and N are integers and M<N. In the method, a plurality of intermediate clock signals are provided having a frequency f
X
, such that
f
X
=
1
X
⁢
f
R
,
wherein X is an integer close in value to N/M, and having a predetermined phase relationship with respect to one another. Selection is made among the intermediate clock signals to provide the output clock signal according to a predetermined sequence applied so as to cause a phase correction at each change of selection such that the cumulative phase correction results in the output clock signal having, on average, the frequency f
O
.
These and other features, aspects and embodiments of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.


REFERENCES:
patent: 5012198 (1991-04-01), Okada et al.
patent: 5271040 (1993-12-01), Clark
patent: 5781054 (1998-07-01), Lee

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