Digital clock skew detection and phase alignment

Details Digital clock skew detection and phase alignment Digital clock skew detection and phase alignment

2000-09-13

2003-09-16

Butler, Dennis M. (Department: 2185)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S401000

Reexamination Certificate

active

06622255

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally related to techniques for phase aligning two digital clock signals.
BACKGROUND
The use of a digital clock signal in electronic systems provides an effective and low cost technique to synchronize events, so that the events can repeat at a high rate dictated by the clock signal. For instance, separate parts of a complex integrated circuit (IC) die may be responsible for generating different portions of a multiple bit value. This multi-bit value may need to be repeatedly read, in a very short time interval, as defined by a reference digital clock signal.
To ensure that the multi-bit value is timely available, multiple copies of the reference clock are generated and fed to the different parts of the IC die using a clock distribution network, so that each part of the IC die provides its portion of the multi-bit value in response to a rising edge of its copy of the reference clock. However, at very high clock rates, variations in the IC die manufacturing process, supply voltage, the operating temperature of the IC die and design mismatches can lead to serious misalignment of corresponding edges in the copies of the reference clock (referred to as “clock skew”), thereby endangering synchronous operation. The design of a robust clock distribution circuit which can operate reliably at very high clock rates is a challenging task that has become a significant portion of the development cost of large, complex IC dies.
A digital phase aligner, such as one based on a delay locked loop (DLL), can be used to automatically decrease clock skew, by for instance adjusting the binary-weighted delay of a variable-delay line to align each output of a clock distribution network to the clock input of an IC die. However, such a circuit may not be space-efficient, such that it might enjoy only limited use in IC dies and printed wiring boards having large clock distribution networks. Moreover, the conventional phase aligner design may not prove to be a sufficiently versatile macro, thus precluding its easy integration in a wide range of applications (beyond deskewing a clock distribution network.) Finally, the phase aligner may not be sufficiently accurate (achieve low skew and jitter) at high clock frequencies.


REFERENCES:
patent: 3989931 (1976-11-01), Phillips
patent: 5121010 (1992-06-01), Hoshizaki et al.
patent: 5455840 (1995-10-01), Nakauchi et al.
patent: 5691656 (1997-11-01), Sandusky
patent: 5748487 (1998-05-01), Sawasaki et al.
patent: 6075832 (2000-06-01), Geannopoulos et al.
patent: 6078634 (2000-06-01), Bosshart
patent: 6265904 (2001-07-01), Killorn
patent: 0 637 137 (1995-01-01), None
Dana Woesta, et al., “Digital-Phase Aligner Macro for Clock Tree Compensation with 70ps Jitter”, ISSCC96/Session 8/Digital Clocks and Latches/Paper FA 8.4.
U.S. patent application Ser. No. 09/094,666, filed Jun. 15, 1998, entitled “Method and Apparatus for Clock Skew Compensation” by Dizon, et al.
U.S. patent application Ser. No. 09/489,153, filed Jan. 21, 2000, entitled “Hierarchical Clock Distribution System for Power-Down of Selective Units in an Integrated Circuit” by Bauer, et al.

Affiliated with

Also associated with

Rating

Digital clock skew detection and phase alignment does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital clock skew detection and phase alignment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital clock skew detection and phase alignment will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3045473