Digital clock recovery PLL

Details Digital clock recovery PLL Digital clock recovery PLL

2006-03-21

2006-03-21

Tse, Young T. (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S326000, C370S518000, C327S144000

Reexamination Certificate

active

07016447

ABSTRACT:
An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to generate an output signal and a clock signal in response to the plurality of samples and the plurality of phases. The clock signal is generally aligned with the output signal.

REFERENCES:
patent: 5127023 (1992-06-01), Tash et al.
patent: 5509037 (1996-04-01), Buckner et al.
patent: 5850422 (1998-12-01), Chen
patent: 5887040 (1999-03-01), Jung et al.
patent: 6031886 (2000-02-01), Nah et al.
patent: 6266799 (2001-07-01), Lee et al.
patent: 6417698 (2002-07-01), Williams et al.
David R. Reuveni, “Digital Clock Recovery PLL”, U.S. Appl. No. 09/822,112, filed Mar. 30, 2001.
David R. Reuveni, “Digital Clock Recovery PLL”, U.S. Appl. No. 09/821,886, filed Mar. 30, 2001.

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