Digital clock recovery circuit

Details Digital clock recovery circuit Digital clock recovery circuit

2007-08-14

2007-08-14

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S375000, C375S327000, C331SDIG002, C331S00100A

Reexamination Certificate

active

10178902

ABSTRACT:
A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.

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