Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-02-06
2002-05-14
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000, C375S376000, C327S158000, C327S159000
Reexamination Certificate
active
06389090
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to digital communications and more specifically to clock and data signal recovery for digital communications.
2. Description of the Prior Art
As is well known in the field of digital (e.g., computer data) communications, two fundamental processes are carried out at the receiver end of a communications system to convert an analog signal transmitted along a communications channel to a digital signal. These processes are (1) analog amplitude domain processing which typically includes signal equalization and slicing in order to produce a discrete level, analog transition time signal; (2) analog transition time processing which typically includes clock signal and data signal recovery to produce a discrete level, discrete time signal; see “A 30-MHz Hybrid Analogy Digital Clock Recovery Circuit in 2-&mgr;mCMOS,” Kim et al.,
IEEE Journal of Solid
-
State Circuits
, SC-25, December 1990, PP. 1385-1394. This disclosure is directed to the latter process.
Note that a discrete level/analog transition time signal has only two voltage levels but can transition between those levels at any time. A discrete level/discrete time signal again has only two voltage levels but can transition between those two levels only at multiples of a time period.
Data recovery is usually achieved by sampling a discrete level/analog-transition-time signal at a rate determined by a recovered clock (timing) signal. There is typically no independent timing signal per se; instead the “clock signal” is inherent in the timing of the data signal pulses. The recovered clock signal therefore is a timing signal generated synchronous to the rate at which the original data pulses were transmitted from the receiver.
See
FIG. 1
showing a conventional digital communications system including, at the receiver end, a D-type flip flop circuit
14
, to the D terminal of which a data signal is coupled via line
10
. The clock input terminal of flip flop
14
is connected via input line
16
to a transmitter (Tx) clock signal. The output signal from flip flop
14
at its Q terminal is coupled via analog processor
20
to a communications channel
22
, for instance a twisted cable pair, coaxial cable etc. Channel
22
may also be for instance an optical fiber link, telephone line, microwave transmission system, etc. (In the optical fiber situation, the analog processor
20
is replaced by an optical transmitter.)
At the distal end of the communications channel
22
the receiver is located which includes an analog processing circuit
26
, as described above including both equalization and slicer functions. The output signal from analog processing circuit
26
is connected to the input terminal of a clock recovery circuit
30
, the output terminal of which is connected to the clock input terminal of a D type flip flop
32
which performs the data recovery function. Line
36
connects the output terminal of the analog processing circuit
26
to the D input terminal of the data recovery flip flop
32
. The recovered data signal is output on the output (Q) terminal of the flip flop
32
.
FIG. 2
relates to
FIG. 1
by showing at each of the designated nodes A, B, C, D, E, F, G in
FIG. 1
, the associated waveform. Node A carries the digital clock signal; node B carries the digital data signal, each pulse of which defines a high and a low state. Node C carries the analog counterpart of the node B signal. Node D carries the received analog signal as distorted by channel
22
. Node E carries the processed received analog signal, including some errors at the transition times (arrows). Node F carries the recovered clock signal and node G the recovered digital data signal.
FIG. 3
shows detail of the clock recovery circuit
30
of
FIG. 1
, illustrating one technique for clock/data recovery which recovers the clock signal using an analog phase-locked loop (PLL) that is locked to the discrete-level/analog-transition-time signal, hereinafter referred to as the analog-transition signal. This recovered clock signal is applied to a flip flop
32
to sample the analog-transition signal. The output of flip flop
32
at node G is the discrete level, discrete time signal hereinafter referred to as a digital signal.
The clock recovery circuit
30
includes a phase detector
40
which generates up or down pulses whose durations are proportional to the phase error between the recovered clock signal and the signal at node E. The output of the phase detector
40
is coupled to a charge pump
44
which in turn is connected via analog filters
46
and
48
to the input terminal of a voltage controlled oscillator (VCO)
54
. The output signal from the VCO
54
is fed back to the other terminal of the conventional phase detector
40
, thus forming the conventional analog phase locked loop. The nodes E, F, A in
FIG. 3
correspond to the similar nodes in FIG.
1
.
The analog PLL, while common, suffers the same disadvantages as most analog circuits, namely: being difficult to manufacture because of process variations, sensitive to system noise, and sensitive to temperature and power supply drift.
SUMMARY
In accordance with this invention, clock and data signal recovery is performed, in one embodiment, without using an analog PLL, and wherein all digital processing is performed at for instance one half the data rate. This is done by providing a digital delay locked loop based on e.g., an off chip reference clock signal. A phase detector, phase pump, and a loop filter are in the delay locked loop, where the phase detector determines for each data pulse's rising (or falling) edge, if the current delay (phase) of the reference clock signal is leading or lagging the data signal edge. The loop filter determines from the stream of lead/lag indicators, by a non-linear digital filtering process, whether it should increase or decrease the delay. The phase pump “holds,” or stores the current reference clock signal phase, until the next update by the loop filter. This advantageously eliminates the VCO from the loop, allows use of digital signal processing, and provides better performance.
In one embodiment the non-linear loop filter is a digital signal processing apparatus and drives a phase pump which in turn outputs a signal to a selector which selects from amongst a number (e.g. 32) of various phases of a clock signal. The phase is selected in response to whether a lead or lag adjustment is necessary. This leading or lagging new clock signal is then fed back to the phase detector and also is used as the clock signal to clock the data recovery circuit.
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patent: 5999027 (1999-12-01), Yamazaki
B. Kim et al., “A 30-Mhz Hybrid Analog/Digital Clock Recovery Circuit in 2-&mgr;m CMOS”, IEEE Journal of Solid-State Circuits, vol. SC-25, pp. 1385-1394, Dec. 1990.
Paist Kenneth
Zortea Anthony E.
3Com Corporation
Chin Stephen
Ha Dac V.
Michaelson Peter L.
Michaelson & Wallace
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