Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-05-11
1999-07-27
Chaudhuri, Olik
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438514, 257390, H01L 21265
Patent
active
059306637
ABSTRACT:
An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.
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Baukus James P.
Chow Lap Wai
Clark Jr. William M.
Chaudhuri Olik
Duraiswamy V. D.
Hughes Electronics Corporation
Sales M. W.
Wille Douglas A.
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