Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-23
2002-09-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06449752
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention relates to the field of digital circuit verification and more particularly to an efficient method for exploring behavior of a digital circuit in the absence of an adequate digital circuit specification.
2. History of Related Art
Digital circuit verification is the process of demonstrating proper behavior of a particular digital circuit implementation. An implementation is behaving properly if the implementation satisfies its specification. Verification is typically accomplished using either simulation or formal verification techniques. Simulation involves running specific tests on a model of the digital circuit implementation to verify proper behavior of the design under the specified test conditions. Formal verification is a process in which the correctness of a design is proven with a rigorous mathematical algorithm. Regardless of the verification technique used, a problem that is pervasive in all verification frameworks is the inability to perform effective verification in the absence of an adequate or comprehensive set of specifications for the circuit under test. If a specification with which the digital circuit under test must comply is missing from the set of specifications available to the verification engineer, no verification framework will be able to detect a violation of this specification. Unfortunately, the desire to reduce the design cycle time in an effort to get new products to market frequently makes it difficult, if not impossible, for the designer of the digital circuit to document a complete or even partial specification for the circuit. Without an adequate specification, the verification process slows significantly as the verification engineer must attempt to piece together a specification against which to test the circuit by simple trial and error and through interaction with the circuit designer. Therefore, it is highly desirable to implement a solution with which a specification for the circuit under test can be systematically and automatically generated such that their verification process would be less dependent on the existence of an adequate design specification. It would be further desirable if the implemented solution effectively shielded the verification process from the details of generating the formula necessary to apply to the digital circuit to derive the specification.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention contemplates a method for automatically and systematically generating a set of specifications against which a model of the digital circuit can be verified. In one embodiment, the method includes an initial step in which a ‘specification class’ that corresponds to a type of behavior of the digital circuit is defined. A set of specification formulae that satisfies the defined specification class is then enumerated. Each formula in the set of formulae is then applied to the model of the digital circuit to determine whether the digital circuit satisfies the corresponding formula. The definition of the specification class preferably includes a set of input conditions, a set of output or response conditions, and a temporal component. Preferably, the enumeration of the specification formulae includes all specification formulae that satisfy the specification class. The application of the set of formulae to the model of the digital circuit is preferably achieved with a verification engine such as a model checker. Preferably, the specification formulae are expressed in temporal logic such as computational tree logic (CTL). In one embodiment the specification formulae are quantified such that the digital circuit satisfies a formula only if the formula always holds true. In another embodiment, the specification formulae are quantified such that the digital circuit satisfies the formula if the formula ever holds true. The preferred embodiment of the invention includes displaying the results achieved by applying the specification formulae to the digital circuit models.
The invention further contemplates a verification system including a graphical user interface for defining a specification class, a model checker or other suitable verification engine, and a wave form viewer. The user interface front-end allows users to define specification classes corresponding to a type of behavior of the digital circuit and then automatically enumerates a set of specification formulae that satisfy the behavior of interest. The enumerator may be implemented as a standalone module or alternatively, the enumerator may be integrated into an existing wave form editor. In the preferred embodiment, the wave form viewer comprises a back-end module of the user interface that allows users to view the results generated by the application of the specification formulae to the digital circuit model. The back-end module permits the user to view a list of the specification formulae generated for the defined specification class. The list preferably includes pass/fail information indicating whether the corresponding specification formula was exhibited or not. The back-end user interface may further include facilities for viewing actual wave form traces. In one embodiment, for example, the interface may include a set of tabs along the top of the viewing window. Each tab corresponds to one of the specification formula. Clicking on the tab for one of the specification formula then permits the viewer to explore the wave form generated on a cycle by cycle for per signal basis. In addition, the back-end user interface may include a tab for viewing a “witness” trace that provides an example of a given behavior or a “counter example” trace demonstrating when a given behavior was violated. The back-end GUI may further encompass a filtering technique for sub-categorizing the formulae in the specification class in which a hierarchical tab-based indexing is used to select between sub-categories. The back-end user interface further includes facilities for storing selected specifications in a storage facility referred to herein as a regression bucket.
REFERENCES:
patent: 5481717 (1996-01-01), Gaboury
patent: 5745712 (1998-04-01), Turpin
Baumgartner Jason Raymond
Malik Nadeem
Roberts Steven Leonard
Do Thuan
Smith Matthew
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