Digital circuit for generating a clock signal

Details Digital circuit for generating a clock signal Digital circuit for generating a clock signal

1995-07-31

1996-07-23

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375355, 326 93, 326 96, H03D 324

Patent

active

055397867

ABSTRACT:
A digital circuit comprising a pair of D Flip-Flops which synchronize an oming NRZ.sub.-- L serial data stream to an external ten megahertz clock signal. The combination of a third D Flip-Flop and an EXCLUSIVE-NOR gate generates a clear pulse whenever a change of state occurs within the synchronized serial data stream. This clear pulse is supplied to a ten state state machine resetting the state machine to state S0. When the state machine transition to state S4 the state machine generates an enable signal which is supplied to a toggle Flip-Flop enabling the Flip-Flop allowing the Flip-Flop to change state. The ten megahertz clock signal then clocks the toggle Flip-Flop causing the Flip-Flop to change state. At state S9 the state machine again provides an enable signal to the toggle Flip-Flop enabling the toggle Flip-Flop which allows the ten megahertz clock signal to change the state of the output of the toggle Flip-Flop. This results in one megahertz clock signal at the output of the toggle Flip-Flop which is synchronized to the incoming serial data stream.

REFERENCES:
patent: 3980820 (1976-09-01), Niemi et al.
patent: 4716578 (1987-12-01), Wight
patent: 5128970 (1992-07-01), Murphy
patent: 5402453 (1995-03-01), Vavreck et al.

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