Digital buffer circuits

Details Digital buffer circuits Digital buffer circuits

1999-05-25

2000-12-19

Tokar, Michael

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 83, 326 86, G11C 800

Patent

active

061631744

ABSTRACT:
CMOS buffer circuits are provided having multiple stages of driving transistors defining a fast "1" data path and a fast "0" data path for transmitting data signals from the input to output of the buffer. Each stage before the last stage in each of the data paths has at least one nulling transistor coupled to the driving transistor of the stage. Separate from the data paths, the nulling transistors of each data path are operated to synchronously null the driving transistors of the data path to prepare such driving transistors for the next fast transition in the input data signal. Another nulling transistor may be also coupled to the driving transistor of each stage before the last stage of each data path which prevents the data path from floating when the data path is not transmitting a transition of the input signal to output of the buffer. The CMOS buffer circuits are suitable for driving large capacitive loads optimally over any range of input signal frequency, restoring slow transitioning digital signals, or driving highly resistive RC interconnect lines.

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