Static information storage and retrieval – Read/write circuit – Noise suppression
Reexamination Certificate
2000-02-18
2001-06-05
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Noise suppression
C365S063000, C365S051000, C257S208000, C257S773000, C257S776000
Reexamination Certificate
active
06243311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory devices and, in particular, the present invention relates to a digit line architecture in a DRAM.
2. State of the Art
A modern DRAM memory cell or memory bit, as shown in
FIG. 1
, consists of one MOS transistor
10
and one storage capacitor
12
—accordingly referred to as a one-transistor one-capacitor (1T1C) cell. The memory bit transistor operates as a switch, interposed between the memory bit capacitor and the digitline
14
. The memory bit is capable of holding a single piece of binary information, as stored electric charge in the cell capacitor. Given a bias voltage of Vcc/2 on the capacitor's common node, a logic one level is represented by +Vcc/2 volts across the capacitor and a logic zero is represented by −Vcc/2 volts across the capacitor. In either case, the amount of charge stored in the memory bit capacitor is Q=C·VCC/2 coulombs, where C is the capacitance value in Farads.
The digitline, as depicted in
FIG. 1
, consists of a conductive line connected to a multitude of memory bit transistors. Generally, either metal or silicided/polycided polysilicon forms the conductive line. Due to the large quantity of attached memory bits, its physical length, and proximity to other features, the digitline is very capacitive. For instance, a typical value for digitline capacitance on a 0.35 &mgr;m process might be around 300 fF. Digitline capacitance is an important parameter since it dictates many other aspects of the design.
The memory bit transistor's gate terminal connects to a wordline (towline)
16
. The wordline, which connects to a multitude of memory bits, consists of an extended segment of the same polysilicon used to form the transistor's gate. The wordline is physically orthogonal to the digitline. A memory array, shown in
FIG. 2
, is created by tiling a selected quantity of memory bits together such that memory bits along a given digitline do not share a common wordline and such that memory bits along a common wordline do not share a common digitline.
FIG. 3
contains an example of a memory array formed by tiling memory bits. There are several features of this layout that need illumination. First, note that the memory bits are in pairs to permit the sharing of a common contact to the digitline. This feature reduces the array size by eliminating unnecessary duplication. Second, note that any given wordline only forms (crosses) a memory bit transistor on alternating digitlines. This feature allows the formation of digitline pairs and ensures that wordline activation enables transistors only on alternate digitlines. Digitline pairs are an inherent feature in folded digitline arrays, as depicted in FIG.
3
. An alternate array structure called open digitline architecture can also be used. A thorough understanding of both folded and open architectures by those skilled in the art assists in appreciating the characteristics and benefits of the bi-level digitline of the present invention. The open digitline and folded digitline architectures both have distinct advantages and disadvantages. While open digitline architectures achieve smaller array layouts by virtue of using smaller 6F
2
memory bit cells, they also suffer from poor noise performance. A relaxed wordline pitch which stems from the 6F
2
memory bit simplifies the task of wordline driver layout. Sense amplifier layout, though, is difficult because the array configuration is inherently half pitch—one sense amplifier for every two digitlines.
Folded digitline architectures, on the other hand, have superior signal to noise, at the expense of larger, less efficient array layout. Good signal to noise performance stems from the adjacency of true and complement digitlines and the capability to twist these digitline pairs. For example, U.S. Pat. No. 5,107,459 to Chu et al., issued Apr. 21, 1992 describes a stacked digitline architecture which uses lateral and vertical twisting. This technique, however, allows differential noise to be experienced on the digitlines which creates difficulty for differential sense amplifiers. Sense amplifier layout in the folded digitline architecture is simplified because the array configuration is quarter pitch—one sense amplifier for every four digitlines. Wordline driver layout is more difficult since the wordline pitch is effectively reduced in folded architectures.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a new array architecture which combines the advantages of both folded and open digitline architectures while avoiding their respective disadvantages. To meet this objective, the architecture needs to include the following features and characteristics: an open digitline memory bit configuration, a small 6F2 memory bit, and a small, efficient array layout. The memory must also include a folded digitline sense amplifier configuration, adjacent true and complement digitlines, and twisted digitline pairs to achieve a high signal to noise ratio. Further, a relaxed wordline pitch should be used to facilitate better layout.
SUMMARY OF THE INVENTION
The above-mentioned problems with digit line architectures and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory device is described which reduces overall die size beyond that obtainable from either the folded or open digitline architectures. A signal to noise performance is achieved which approaches that of the folded digitline architecture.
In particular, the present invention describes a dynamic memory device comprising a multilevel digit line pair fabricated on a semiconductor die. The multi-level digit line pair has vertically offset first and second digit lines. The digit line pair is vertically twisted such that the first digit line is located below the second digit line on one horizontal side of the vertical twist and located above the second digit line as upper digit line on an opposite horizontal side of the twist.
In another embodiment, an integrated circuit dynamic memory device comprises an integrated circuit die having multiple, vertically offset conductive levels, and a multi-level digit line pair fabricated on the integrated circuit die having first and second electrically isolated digit lines, each of the first and second digit lines comprising first and second sections located in different ones of the multiple conductive levels and electrically connected via a vertically traversing electrical path. The first and second digit lines are located such that the first section of the first digit line is vertically located above the first section of the second digit line and the second section of the first digit line is vertically located below the second section of the second digit line.
In yet another embodiment, a method is described for reducing noise in an integrated circuit memory device. The method comprises the step of electrically balancing first and second vertically stacked digit lines. To balance the digit lines, the first and second digit lines can be fabricated in first and second conductive levels such that the first and second digit lines are substantially vertically aligned. A vertical conductive twist can be provided to locate a portion of each of the first and second digit lines in both the first and second conductive levels. Finally, an equal number of memory cells can be coupled to the portion of the first and second digit line located in a lower conductive level.
REFERENCES:
patent: 4536947 (1985-08-01), Bohr et al.
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4914502 (1990-04-01), Lebowitz et al.
patent: 4922460 (1990-05-01), Furutani et al.
patent: 4967396 (1990-10-01), Kajigaya et al.
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5014110 (1991-05-01), Satoh
patent: 5107459 (1992-04-01), Chu et al.
pat
Micro)n Technology, Inc.
Nguyen Viet Q.
TraskBritt
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