Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
2003-03-06
2004-10-26
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S922000, C438S923000, C438S933000, C438S486000, C257SE31035
Reexamination Certificate
active
06809016
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to high speed, high performance MOS semiconductor devices, particularly NMOS transistors, fabricated on strained lattice semiconductor substrates. The present invention has particular applicability in fabricating NMOS transistors on strained lattice semiconductor substrates having reduced punch-through in the silicon-geranium (SiGe) layer.
BACKGROUND OF THE INVENTION
The increasing demand for micro-miniaturization requires scaling down various horizontal and vertical dimensions of various device structures. Smaller devices typically equate to faster switching times which lead to faster devices with high performance. Source/drain extensions with abrupt junctions/dopant profile slopes in proximity to the transistor channel are required to reduce penetration of the source/drain dopant into the transistor channel which occurs as the junction/profile slope becomes less abrupt. Such short channel effects result in poor threshold voltage roll-off characteristics for submicron devices.
Attempts to fabricate semiconductor with higher operating speeds, enhanced performance characteristics, and lower power consumption have led to the development of “strained silicon”. According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition of SiGe buffer layer several microns thick, which SiGe buffer layer is, in turn, formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. The SiGi layer typically contains about 0.15 to 0.25 at % Ge. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the SiGe buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on the SiGe substrate comprised of atoms which are spaced further apart than in pure Si, they “stretch” to align with the underlying lattice of Si and Ge atoms, thereby “stretching” or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
In attempting to fabricate NMOS devices on strained silicon substrates using arsenic (As) as the dopant, punch-through difficulties have been encountered, primarily because As exhibits very rapid diffusion in SiGe vis-à-vis Si. Such rapid diffusion undesirably distorts the originally formed junction shape generating short channel effects.
Accordingly, a need exists for methodology enabling the fabrication of semiconductor devices based on strained silicon substrates having reduced short channel effects, notably punch-through in the SiGe layer. There exists a particular need for methodology enabling the fabrication of NMOS transistors implanted with As and having reduced short channel effects.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having an NMOS transistor doped with As over a strained silicon substrate having reduced short channel effects.
Another advantage of the present invention is a semiconductor device having an NMOS transistor doped with arsenic on a strained silicon substrate having reduced short channel effects.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointing out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved by a method of manufacturing a semiconductor device, the method comprising: forming a substrate comprising a semiconductor layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (SiGe); forming a gate electrode, with side surfaces, on an upper surface of the substrate with a gate dielectric layer therebetween; ion implanting arsenic (As) into the substrate to form source/drain extension implants having junctions with the strained Si and SiGe layers under the side surfaces of the gate electrode; ion implanting boron impurities into the substrate at the junctions to form diffusion stop implants which inhibit diffusion of As; and heating to form activated As source/drain extensions, wherein the diffusion stop implants prevent As diffusion during heating.
Embodiments of the present invention comprise ion implanting boron ions at an angle of 10° to 45° with respect to a line perpendicular to the substrate surface to form the diffusion stop implants either before or after forming the As source/drain extensions implants. Sidewall spacers are then formed on the side surfaces of the gate electrode and deep As source/drain implants are formed. Annealing is then conducted, as at a temperature 1000° C. to 1100° C. for 1 second to 10 seconds, to activate the As source/drain extensions and deep As source/drain regions.
Another aspect of the present invention is a semiconductor device having an N-channel resistor comprising: a substrate comprising a semiconductor layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (SiGe); a gate electrode, with side surfaces, on an upper surface of the substrate with a gate dielectric layer therebetween; source/drain extensions containing arsenic (As) in the substrate having junctions with the strained Si and SiGe layers under the side surfaces of the gate electrode; and diffusion stop implants containing boron at the junctions. Embodiments include such semiconductor devices wherein the diffusion stop implants contain boron at a concentration of 5×10
17
to 1×10
19
atoms/cm
3
.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.
REFERENCES:
patent: 6080614 (2000-06-01), Neilson et al.
patent: 6380036 (2002-04-01), Oda et al.
patent: 6472281 (2002-10-01), Doi et al.
patent: 6670682 (2003-12-01), Mouli
patent: 6723621 (2004-04-01), Cardone et al.
patent: 2003/0062537 (2003-04-01), Sugii et al.
Advanced Micro Devices , Inc.
Fourson George
Pham Thanh V
LandOfFree
Diffusion stop implants to suppress as punch-through in SiGe does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Diffusion stop implants to suppress as punch-through in SiGe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Diffusion stop implants to suppress as punch-through in SiGe will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3326054