Diffusion replica delay circuit

Details Diffusion replica delay circuit Diffusion replica delay circuit

2001-02-02

2003-08-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S210130, C365S150000

Reexamination Certificate

active

06611465

ABSTRACT:

The following related patent applications, assigned to the same assignee hereof and filed on even date herewith in the names of the same inventors as the present application, disclose related subject matter, with the subject of each being incorporated by reference herein in its entirety:
Memory Module with Hierarchical Functionality, Attorney Docket No. 40050/B600/JFO; High Precision Delay Measurement Circuit, Attorney Docket No. 37079/B600/JFO; Single-Ended Sense Amplifier with Sample-and-Hold Reference, Attorney Docket No. 37362/B600/JFO; Limited Switch Driver Circuit, Attorney Docket No. 37361/B600/JFO; Fast Decoder with Asynchronous Reset with Row Redundancy; Attorney Docket No. 37115/B600/JFO; Diffusion Replica Delay Circuit, Attorney Docket No. 37360/B600/JFO; Sense Amplifier with Offset Cancellation and Charge-Share Limited Swing Drivers, Attorney Docket No. 37363/B600/JFO; Memory Architecture with Single-Port Cell and Dual-Port (Read and Write) Functionality, Attorney Docket No. 37364/B600/JFO; Memory Redundancy Implementation, Attorney Docket No. 37496/B600/JFO; and; A Circuit Technique for High Speed Low Power Data Transfer Bus, Attorney Docket No. 37497/B600/JFO.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory devices, in particular, semiconductor memory devices, and most particularly, scalable, power-efficient semiconductor memory devices.
2. Background of the Art
Memory structures have become integral parts of modern VLSI systems, including digital signal processing systems. Although it typically is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory system and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (SRAM), which can retain its memory state without the need for refreshing as long as power is applied to the cell. In an SRAM device, the memory state II usually stored as a voltage differential within a bistable functional element, such as an inverter loop. A SRAM cell is more complex than a counterpart dynamic RAM (DRAM) cell, requiring a greater number of constituent elements, preferably transistors. Accordingly, SRAM devices commonly consume more power and dissipate more heat than a DRAM of comparable memory density, thus efficient; lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density SRAM components, providing those memory components observe the often strict overall design constraints of the particular VLSI system. Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptions of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be “scalable”, often fail to meet design limitations once these memory subsystem designs are scaled-up for use in a VLSI system with need for a greater memory cell population and/or density.
There is a need for an efficient, scalable, high performance, low-power memory structure that allows a system designer to create a SRAM memory subsystem that satisfies strict constraints for device area, power, performance, noise sensitivity, and the like.
SUMMARY OF THE INVENTION
The present invention satisfies the above needs by providing a diffusion replica delay circuit substantially replicates a delay characteristic of a predetermined memory structure component, for example, a bitline, so that a localized timing signal can be generated, thus providing high-localized decision making, e.g., permitting independent operation of, and access to, memory structure rows. One embodiment of this aspect of the invention includes a diffusion replica capacitor, which is capable of storing within the diffusion replica capacitance, a predetermined replica charge representative of, and generally matched to, a selected memory component operational characteristic. For example, the diffusion replica capacitance can be a predetermined fraction of the total memory component capacitance. Where the memory component includes a multiple access transistors with an access chain characteristic, the diffusion replica transistor is disposed to be representative of the access chain characteristic. The diffusion replica transistor can be coupled between the diffusion replica capacitor and a charge sink, and is disposed to control the magnitude of the predetermined replica charge. Certain embodiments of this aspect of the invention include a dummy cell with a dummy bit line and a plurality of wordlines, with the diffusion replica capacitor being coupled to the split dummy bit line and a limited number of wordlines, preferably one wordline. One such memory component characteristic can be a dummy bitline capacitance of a bitline, coupled to the diffusion replica delay circuit, with the diffusion replica capacitance being substantially matched to, and is preferred to be, a predetermined fraction of the dummy bitline capacitance. One or more dummy cell each can be coupled with one or more memory cells, having local bitlines and local wordlines. The diffusion replica delay circuit provides a limited voltage swing signal the local bitlines, the local wordlines, or both. It is preferred that dummy cells be selectively coupled with memory cells, each having local bitlines and local wordlines, with particular dummy cell being coupled with a selected local wordline decoder and a selected local sense amplifier. Also, a split dummy bitline can be associated with a particular wordline, obviating the excess delay from grouped wordline association.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the following drawings.


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Kiyoo Itoh et al., “Trends in Low-Power RAM Circuit Technologies,” Proceedings of the IEEE, Apr. 1995, pp. 524-543, vol. 83, No. 4, IEE.

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