Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-12-30
2004-06-29
Wilson, Allan R. (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S750000, C257S752000, C438S653000
Reexamination Certificate
active
06756303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Preferred embodiments of the invention pertain to the prevention of diffusion of copper into a surrounding dielectric in an integrated circuit.
2. Related Technology
Integrated circuits (ICs) are manufactured by forming discrete semiconductor devices such as MOSFETS and bipolar junction transistors on a semiconductor substrate, and then forming a back end metal wiring network that connects those devices to create circuits. The wiring network is composed of individual metal wires called interconnects that generally lay parallel to the plane of the substrate. Interconnects are connected to the semiconductor devices by vertical contacts and are connected to other interconnects by vertical vias. A typical wiring network employs multiple levels of interconnects and vias.
The performance of integrated circuits is determined in large part by the conductivity and capacitance of the wiring network. Copper (Cu) has been adopted as the preferred metal for wiring networks because of its low resistivity compared to other conventional metals such as tungsten (W) and aluminum (Al), and because of its low cost compared to other low resistivity metals such as silver (Ag) and gold (Au). High quality Cu is also easily formed by damascene (inlay) processing using wet plating techniques such as electroplating or electroless plating followed by annealing.
Although Cu provides the aforementioned desirable features, it also has detrimental characteristics that must be addressed in order to produce functional products. One problem with Cu is its tendency to diffuse into surrounding semiconductor and insulating substrate materials. This diffusion degrades the semiconductive or insulative properties the surrounding material, and also affects the adhesion of the copper to the substrate. As a result, it is now conventional to provide a diffusion barrier between the copper and surrounding material.
FIG. 1
shows an example of a conventional copper via
10
. The via is formed in a substrate that includes an interlevel dielectric (ILD) layer
12
. The via
10
is inlaid in a trench that extends through the ILD
12
to contact an underlying conductive element
14
such as an interconnect. The copper material of the via
10
is surrounded by a diffusion barrier
16
that is formed as a conformal layer over the substrate to line the trench prior to inlaying of the via material. The diffusion barrier
16
prevents diffusion of copper from the via
10
into the surrounding ILD material
12
. Conventional Cu diffusion barrier materials include titanium (Ti), titanium nitride (TiN), tungsten (W), chromium (Cr), tantalum (Ta), and tantalum nitride (TaN). The substrate and the upper surface of the via are protected by a passivation material
18
, which is typically a layer of dielectric material such as silicon nitride (SiN) that covers the entire substrate. In some instances, selectively deposited metal is used as a passivation material.
The barrier materials listed above are preferred over other diffusion barrier materials such as SiN because they are conductive and may therefore be located in the conductive path of the conductive element. For example, referring to
FIG. 1
, the conformally deposited diffusion barrier
16
may be left at the bottom of the trench between the via
10
and the interconnect
14
because it is able to conduct current between those two elements, whereas an insulating barrier material such as SiN would have to be removed from the bottom of the trench prior to formation of the via
10
in order to provide a conductive path. Such removal requires masking of the substrate and exposing only the trench bottoms to an etching agent. Such processing is exacting and time consuming, and becomes more difficult as critical dimensions continue to shrink.
While conductive diffusion barriers are presently the preferred diffusion barrier materials, they do not provide as much diffusion protection as insulative barrier materials such as SiN. As critical dimensions continue to shrink, the thickness of diffusion barriers must also be reduced, however thinner diffusion barriers provide less protection against diffusion. Thus there is an incentive to enhance the diffusion protection provided by conventional conductive barrier materials, for example, TiN may be enhanced by doping with silicon (Si). However, such enhancing materials tend to increase the resistance of the diffusion barrier, leading to the problems discussed above regarding insulating diffusion barriers.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, a conductive diffusion barrier is doped with one or more diffusion barrier enhancing materials through a low energy implantation process. The implantation is performed at an angle with respect to the broad surface of the substrate so that the sidewalls of the trench protect the bottom of the trench from being implanted. In this manner, the barrier properties of the sidewalls are enhanced, and the conductive properties of the barrier at the bottom of the trench are not degraded. This processing may be performed with any conventional trench structure such as a via, an interconnect, or a dual damascene structure. Any of a variety of conductive barrier materials and any of a variety of barrier enhancement materials may be employed.
In accordance with another preferred embodiment of the invention, a conductive element in the back end wiring network of an integrated circuit is surrounded by a diffusion barrier. The diffusion barrier is comprised of a conductive diffusion barrier material. The sidewall portion of the diffusion barrier is comprises the conductive diffusion barrier material and a diffusion barrier enhancing material, while the bottom of the diffusion barrier comprises the conductive diffusion barrier material but not the diffusion barrier enhancing material.
REFERENCES:
patent: 5118636 (1992-06-01), Hosaka
patent: 5278438 (1994-01-01), Kim et al.
patent: 5498564 (1996-03-01), Geissler et al.
patent: 6107153 (2000-08-01), Huang et al.
patent: 03087023 (1991-04-01), None
Erb Darrell M.
Wang Fei
Advanced Micro Devices , Inc.
Foley & Lardner LLP
Wilson Allan R.
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