Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-05
2004-12-07
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S019000, C257S192000, C257S194000, C257S285000, C257S616000
Reexamination Certificate
active
06828628
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more particularly to diffused metal oxide semiconductor (MOS) devices.
BACKGROUND OF THE INVENTION
One type of diffused metal oxide semiconductor (MOS) device is a double-diffused MOS (DMOS) device, which has gained popularity in certain applications for high power capabilities. There are various types of DMOS devices, such as Lateral DMOS (LDMOS) devices, vertical DMOS devices, and trench DMOS devices. In an LDMOS device, the gate is placed adjacent the source region, which is a highly doped region created via a diffusion and which normally is connected to a conductor to form the source of the LDMOS device. The drain, which also comprises a highly doped drain region and a conductor connected thereto, is placed some distance away from the gate. The gate is formed on a surface of a semiconductor region, while the source and drain regions are formed under the surface of the semiconductor region. Between the gate and the drain region are one or more lightly doped diffusion areas, generally called a lightly doped drain (L
DD
). Because an LDMOS device has drain regions at the top surface of a semiconductor region, the LDMOS device tends to occupy a larger surface area as compared to other DMOS devices.
Vertical and trench DMOS devices, for example, tend to occupy a smaller surface area than LDMOS devices because their drain regions are vertically situated. In both vertical and trench DMOS devices, the source region or regions and gate are formed near a top surface of a semiconductor region and the drain region is formed on a lower surface of a semiconductor region or formed as a buried layer. Because the source and drain regions are vertical with respect to the top surface of the semiconductor region, a higher density, as compared to LDMOS, may be achieved. However, this density can come at the cost of increased manufacturing complexity. By way of example, a trench DMOS device has a trench in which the gate is formed. The gate is surrounded by a relatively thin layer of insulator on at least three sides of the gate. Formation of the gate and insulator in the trench requires multiple processing steps.
One distinguishing feature of a DMOS device, as compared to, for example, a complementary MOS (CMOS) device, is a body that is diffused from the source side only and that underlies the gate of the DMOS device. The body also underlies the source region, and the body is a different conductivity type than the conductivity type of the source and drain regions. Two diffusions are generally used to form the body and one or both of the source and drain regions: one diffusion is used to form the body and another diffusion forms one or both of the source and drain regions. Thus, the term “double-diffused” is used to describe these MOS devices. Another feature of DMOS devices is a drift region. The drift region is characterized, in a forward conduction mode of the DMOS device, by carriers “drifting” under the influence of an electric field. The drift region is generally formed from a single, lightly doped region between the drain region and the gate. However, there are certain devices that use multiple layers to form a drift region. An example is called a “superjunction” structure. The drift region allows a voltage drop to occur so that a DMOS device can sustain a higher voltage than other semiconductor devices, such as CMOS devices.
Although DMOS devices provide substantial voltage handling and other benefits, as compared to CMOS devices, there is still a need to further improve conventional DMOS devices.
SUMMARY OF THE INVENTION
The present invention provides diffused metal oxide semiconductor (MOS) devices having strained silicon portions and techniques for forming the same.
In accordance with one aspect of the invention, a diffused MOS device is formed comprising source and drain regions, both of a first conductivity type and formed in a semiconductor region. The DMOS device also comprises a gate proximate the source region. The DMOS device further comprises a body of a second conductivity type and formed in the semiconductor region. The body at least partially overlaps the source region and at least partially overlaps the gate, and the body forms at least a portion of a carrier transit path between the source region and the drain region. Additionally, one or more strained silicon portions are formed at least in part in the carrier transit path.
The one or more strained silicon portions may comprise a layer of strained silicon, generally formed above a layer of lattice mismatch material such as silicon germanium or silicon carbide. The carrier transit path may include other regions, such as a diffusion area, channel region, or accumulation region. Additionally, the one or more strained silicon portions may be formed only in selected regions of the DMOS device or may be formed throughout a large portion of the DMOS device.
In accordance with a further aspect of the invention, the one or more strained silicon portions may be formed through the patterning of a hard mask, forming a lattice mismatch layer on the patterned hard mask, forming a strained silicon layer on the lattice mismatch layer, and removing the hard mask. Trenches may also be formed prior to forming the lattice mismatch material on the patterned hard mask.
In another aspect of the invention, multiple different types of DMOS devices may be created, such as lateral DMOS devices, vertical DMOS devices, and trench DMOS devices.
In accordance with a further aspect of the invention, DMOS devices having strained silicon portions may also be integrated with other devices, such as complementary MOS (CMOS) devices or bipolar junction transistor devices.
REFERENCES:
patent: 5776812 (1998-07-01), Takahashi et al.
patent: 5780324 (1998-07-01), Tokura et al.
patent: 6107661 (2000-08-01), Okabe et al.
patent: 2002/0030227 (2002-03-01), Bulsara et al.
patent: 2002/0125471 (2002-09-01), Fitzgerald et al.
“Amberwave and Aixtron to Develop CVD Equipment for SiGe and Strained Si,” http://www.compoundsemiconductor.net/articles
ews (May 17, 2002).
Huang et al., “Carrier Mobility Enhancement in Strained Si-On-Insulator Fabricated by Wafer Bonding,” Symp. on VLSI Technology, 59 (2001).
Lammers, D., “AmberWave Strained-Silicon Process Removes Troublesome SiGe Layer,” Electronic Engineering Times (Oct. 21, 2002).
Murphy, T., “Intel Strains to Pull Ahead—Process Technology Disclosure Raises Eyebrows” Electronic News, p. 14 (Aug. 19, 2002).
Rim et al., “Strained Silicon NMOSFETs for High Performance CMOS Technology,” Symp. on VLSI Technology, 59 (2001).
Hergenrother John Michael
Shibib Muhammed Ayman
Xie Zhijian
Xu Shuming
Agere Systems Inc.
Wojciechowicz Edward
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