Fishing – trapping – and vermin destroying
Patent
1986-03-03
1988-06-07
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 70, H01L 2176
Patent
active
047496622
ABSTRACT:
The present invention is a CMOS process for forming an N-channel device and a P-channel device on a doped substrate wherein an active region surrounded by field for the N-channel device is delineated to comprise a thin layer of oxide, a layer of nitride and a further layer of oxide. An active region surrounded by field of the P-channel device is delineated to comprise a thin layer of oxide and a layer of nitride. A well beneath the P-channel active region and the surrounding field region therefor is implanted. Then, the N-channel field is implanted. The oxide layer is removed from the N-channel active region and field oxide is grown for both channels while the well implant and the field implant are concurrently driven-in. The nitride layers are removed, and sacrificial oxide is grown and removed. Implanting is carried out for threshold adjust. The gate oxide is grown, and the gate electrodes of doped polysilicon are delineated for each channel. An activated source and drain is established for each channel. The crossover oxide is deposited, and metal contacts are established to each source and drain and to the gate polysilicon through the crossover oxide.
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"VLSI Fabrication Principles", S. K. Ghandhi, 1983, John Wiley & Sons, pp. 386, 328, 557, 580.
Caldwell Wilfred G.
Hamann H. Fredrick
Hearn Brian E.
Montanye George A.
Quach T. N.
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