Differential via pair impedance verification tool

Details Differential via pair impedance verification tool Differential via pair impedance verification tool

2005-05-03

2005-05-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06889367

ABSTRACT:
A computer-implemented method is disclosed for verifying impedance in a differential via pair. A target differential via pair is identified in a design database. A desired modal characteristic impedance for the target differential via pair is obtained. A two-dimensional window is established around the differential via pair in which neighboring vias will be included in a modal characteristic impedance calculation for the target differential via pair. A modal characteristic impedance for the target differential via pair is calculated based at least in part on the neighboring vias in the two-dimensional window. The target differential via pair is flagged if the calculated modal characteristic impedance does not match the desired modal characteristic impedance.

REFERENCES:
patent: 6381730 (2002-04-01), Chang et al.
patent: 6530062 (2003-03-01), Liaw et al.
patent: 6769102 (2004-07-01), Frank et al.
patent: 6807650 (2004-10-01), Lamb et al.

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