Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1998-12-28
2001-03-27
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000
Reexamination Certificate
active
06208161
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a differential signal transmission circuit for transmitting a high speed pulse signal through a differential transmission line, and more particularly, to a differential signal transmission circuit to be used in a semiconductor test system in which a differential type CMOS circuit directly drives a differential transmission line formed of a pair of coaxial cables or twisted pair lines.
BACKGROUND OF THE INVENTION
In testing high speed electrical devices such as LSI and VLSI circuits, a semiconductor test system must have high speed signal transmission circuits for sending high speed test signals from a main frame to a test head or receiving response signals of a device under test (DUT) sent from the test head to the main frame. In many situations, such signal transmission is performed in a differential mode in which two signals, each being applied between an input terminal and a common ground, i.e., balanced with one another, are amplified and transmitted.
An example of circuit arrangement in a differential signal transmission circuit is shown in
FIGS. 5
,
6
and
7
for transmitting high speed pulse signals. An example of
FIG. 6
has n channels of transmission circuits. In this example, the differential signal transmission circuit is configured with output buffers
11
1
-
11
n
, ECL (Emitter-Coupled Logic) differential drivers
12
1
-
12
n
, sender resistors
13
1
-
13
n
, transmission cables
14
1
-
14
n
, receiver resistors
15
1
-
15
n
, differential receivers
16
1
-
16
n
.
Pulse widths of the high speed pulse signals in such an application of a high speed semiconductor test system are as narrow as several hundred pico-seconds. The pulse waveform reproduced at the output of the differential receiver
16
needs to maintain the high timing resolution in the original pulse signal with respect to the leading edge and trailing edge (rising and falling edges) of the pulse waveform. Further, the reproduced pulse waveform must not have jitters in the rising edge and falling edge thereof.
The output buffer
11
is a CMOS buffer provided at the output stage of an LSI circuit to interface with an ECL level of the ECL differential driver
12
. A plurality of output buffers
11
1
-
11
n
may be provided at the output of the LSI circuit to receive high speed pulse signals from he LSI circuit and convert the logic levels of the pulse signals to an ECL level to be received by the ECL differential drivers
12
1-12
n
. Examples of the output buffers are, PECL (Positive Emitter Coupled Logic), PCML (Pseudo Current Mode Logic) and LVDS (Low Voltage Differential Signal), all of which are CMOS drivers but with ECL voltage swings.
The transmission cables
14
1
-
14
n
are, for example, differential coaxial cables for propagating high frequency signals therethrough. A typical characteristic impedance of the coaxial cable is 110 ohms. In the application of a semiconductor test system, the transmission cables
14
1
-
14
n
connect between the main frame and test stations of the semiconductor test system. In such an application, the length of the transmission cables is 5 meters or more.
The ECL drivers
12
1
-
12
n
are differential type drivers which receive the high speed pulse signals from the output buffers
11
1
-
11
n
to drive the transmission cables
14
1
-
14
n
. The output impedance Z
out
of the ECL drivers
12
is several ohms which is substantially lower than the characteristic impedance of the transmission cables
14
. Each of the sender resistors
13
1
-
13
n
includes pull down resistors of several hundred ohms connected to a voltage source V
EE
as shown in FIG.
6
. The sender resistor
13
further includes a series termination circuit
13
ST
each of which having a pair of series resistor R
1
and a peaking circuit. Each of the peaking circuits is formed of a resistor RP
2
and a capacitor CP
2
as shown in FIG.
7
.
The series resistor R
1
in the series termination circuit
13
1ST
has an impedance of around 50 ohms so that the sum of the impedance R
1
and the Z
out
of the ECL differential driver
12
is equal to a half of the characteristic impedance (110 ohm) of the transmission cable
14
. This impedance arrangement can effectively terminate and thus absorb a reflected signal from the differential receiver
16
by the sum of the series resistors R
1
and the output impedance Z
out
of the ECL differential buffer
14
.
As known in the art, the peaking circuit is used in a high speed pulse transmission circuit to compensate or enhance high frequency components in the pulse signal to maintain the sharpness of the rising and falling edges of the pulse signal. The example of
FIG. 7A
is a first order peaking circuit having the peaking resistor RP
2
and the peaking capacitor CP
2
connected in series.
FIG. 7B
shows another example of peaking circuit which is formed of a first order peaking circuit having a peaking resistor RP
2
and a peaking capacitor CP
2
connected in series as well as a second order peaking circuit having a peaking resistor PR
3
and a peaking capacitor PC
3
connected in parallel.
Each of the receiver resistors
15
1
-
15
n
is a pair of parallel resistors for terminating the transmission cable
14
at the input of the differential receiver
16
. The impedance of each of the parallel resistors is, for example, around 55 ohms. The parallel resistors are connected to the ground through a capacitor as shown in FIG.
6
. In receiving the differential pulse signals, the differential receivers
16
1
-
16
n
reproduce the transmitted pulse signals at their outputs.
In the conventional differential signal transmission circuit as described above, the ECL differential drivers
12
drive the transmission cables
14
to send the pulse signals. The reason for requiring the ECL differential drivers
12
in this arrangement is that the output buffers
11
in the LSI circuit do not have output impedance small enough to mach the characteristic impedance of the transmission cables
14
.
Typically, a semiconductor test system has high speed pulse signal transmission channels of several hundreds or more. Thus, in such an application of the semiconductor test system, a large number of ECL differential drivers must be mounted on a printed circuit board at the output of the LSI circuit as shown in FIG.
5
. Since the conventional technology requires a large number of ECL drivers, it is disadvantages because it involves the increase of power consumption, increase in the space in the printed circuit board, and the increase in the cost.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a differential signal transmission circuit in which CMOS (Complementary Metal Oxide Semiconductor) driver circuits having relatively high output impedance provided at the output of the LSI circuit directly drive the transmission cables.
It is another object of the present invention to provide a differential signal transmission circuit in which CMOS driver circuits which directly drive the transmission cables are integrated in an LSI circuit.
It is a further object of the present invention to provide a differential signal transmission circuit which can obviate the use of ECL differential drivers in driving the transmission cables for transmitting high speed pulse signals.
It is a further object of the present invention to provide a differential signal transmission circuit which is capable of decreasing the power consumption, the space in the printed circuit board, and the production cost.
In the differential signal transmission circuit of the present invention, CMOS (Complementary Metal Oxide Semiconductor) drivers directly drive differential transmission cables for transmitting high speed signals therethrough. The differential signal transmission circuit is comprised of a CMOS differential driver for receiving a high speed signal to be transmitted from an LSI circuit and providing the signal to a differential transmission cable, an impedance matching circuit provided at an output of the CMOS differential driv
Advantest Corp.
Muramatsu & Associates
Tokar Michael
Tran Anh
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