Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent
1997-05-30
1999-11-16
Tokar, Michael
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
326 83, 326 86, H03K 19003, H03K 1716
Patent
active
059864630
ABSTRACT:
The different signal generation circuit has a first transistor MP2 connected between a first power supply line Vcc and a first output terminal OTP and a gate connected to a first node, a second transistor MN2 connected between the first output terminal OTP and a second power supply line GND and a gate connected to a second node, and a delay circuit 31 and 13 connected between the first node and the second node.
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H. Kohno et al., "A 350-MS/s 3.3-V 8-bit CMOS D/A Converter Using a Delayed Driving Scheme", IEEE 1995 Custom Integrated Circuits Conference, pp. 211-214.
Le Don Phu
NEC Corporation
Tokar Michael
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