Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-12-19
2001-07-03
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S210130, C365S208000, C365S207000, C365S206000, C365S173000, C365S171000, C365S148000, C365S158000, C365S190000, C365S189070
Reexamination Certificate
active
06256247
ABSTRACT:
BACKGROUND
The present invention relates to information storage devices. More specifically, the present invention relates to sense amplifiers for resistive cross point memory cell arrays.
Consider the example of a Magnetic Random Access Memory (“MRAM”) device including a resistive cross point array of spin dependent tunneling (SDT) junctions, word lines extending along rows of the SDT junctions, and bit lines extending along columns of the SDT junctions. Each SDT junction memory cell element is located at a cross point of a word line and a bit line. The magnetization of each SDT junction assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1.’ The magnetization orientation, in turn, affects the resistance of the SDT junction. Resistance of the SDT junction is a first value (R) if the magnetization orientation is parallel and a second value (R+&Dgr;R) if the magnetization orientation is anti-parallel. The magnetization orientation of the SDT junction and, therefore, its logic value may be read by sensing its resistance state.
Sensing the resistance state of a single SDT junction in the array can be unreliable. All SDT junctions in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the SDT junction at that cross point in parallel with resistances of SDT junctions in the other rows and columns (the array of SDT junctions may be characterized as a cross point resistor network).
Moreover, small differences inherent in sense amplifiers can lead to small differential voltages applied to the resistive cross point array when attempting to sense a single SDT junction. These small differential voltages can give rise to parasitic or “sneak path” currents. The parasitic currents can interfere with the sensing of the resistance states.
There is a need to reliably sense the resistance states of SDT junctions in MRAM devices. More generally, there is a need to reliably sense resistance states of memory cell elements in resistive cross point memory cell arrays.
SUMMARY
According to one aspect of the present invention, a read circuit for a resistive cross point memory cell array includes a differential amplifier having first and second input nodes; a first direct injection preamplifier coupled to the first input node of the differential amplifier; and a second direct injection preamplifier coupled to the second input node of the differential amplifier. Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.
REFERENCES:
patent: 4633443 (1986-12-01), Childers
patent: 5831920 (1998-11-01), Chen et al.
patent: 5898612 (1999-04-01), Chen et al.
patent: 5982658 (1999-11-01), Berg et al.
patent: 1003176A2 (2000-05-01), None
English translation of EP1003176A2, May 24, 2000, pp. 1-22.
Hewlett-Packard Co
Tran Andrew Q.
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