Differential read and write architecture

Details Differential read and write architecture Differential read and write architecture

2009-09-11

2011-12-13

Dinh, Son (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S173000

Reexamination Certificate

active

08077501

ABSTRACT:
A memory cell includes a pair of magnetic tunnel junctions and a pair of associated transistors. The magnetic tunnel junctions of the pair are differentially disposed so that in response to the applied voltages, when one them stores a logic one, the other one stores a logic zero. Accordingly, the read operation margin is increased by a factor of two. The true and complementary bit lines of the differential memory cell are coupled to a sense amplifier. Consequently, the need for using reference bit lines is eliminated.

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Notice of Allowance for U.S. Appl. No. 12/544,189, mailed on Aug. 24, 2011.

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