Differential output driver

Details Differential output driver Differential output driver

2002-10-30

2004-05-11

Le, Don (Department: 2812)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S083000, C326S086000

Reexamination Certificate

active

06734700

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a differential output driver, and more particular to a differential output driver which is applied to a transmission terminal of a USB (universal Serial Bus) interface.
BACKGROUND OF THE INVENTION
Generally, a conventional taper buffer, as shown in
FIG. 1A
, is only a simply digital design without any compensation to the process. Thus, this kind of circuits contributes to the variation of the process greatly. For example, when using a simulation program (e.g. H-spice) to simulate the circuit under the condition that the voltage of PTNT (PMOS set as typical and NMOS set as typical) is 3.3 Volt, the crossover voltage and rise/fall time (T
r
/T
f
, T
r
=T
f
) are adjusted as 1.65 Volt and
6
n sec respectively. However, under the conditions of the output loading and the output voltage are identical, e.g. PFNS (PMOS set as fast, and NMOS set as slow) and PSNF (PMOS set as slow and NMOS set as fast), the crossover voltage might be altered to range between 1.2 and 2.05 Volt and the specific value of the rise/fall time will becomes larger than 1.1 or smaller that 0.9, e.g. T
r
=7n sec, T
f
=5n sec and the crossover voltage will also range between 1.2 and 2.05 Volt. When the rise/fall time of the input control signal D
in
+
/D
in
−
are set as identical, as shown in
FIG. 1B
, and the process is set as PTNT, by executing the simulation program (e.g., H-spice), the simulation result is T
r
=T
f
and the crossover voltage=V
DD
/2 (as shown in FIG.
1
C). When the process is set as PFNS or PSNF, by executing the simulation program (for simulating the error caused by the shift in the process), the simulation result is T
r
T
f
and the crossover voltage is not V
DD
/2 any longer (as shown in FIGS.
1
D and
1
E).
For solving the problem described above, a compensational differential output driver is developed. As shown in
FIG. 2
, the circuit structure includes a current source, a first current mirror set, a second current mirror set, a first output buffer, and a second output buffer. However, the first current mirror set includes transistors MP
1
and MP
2
. The second current mirror set includes transistors MN
1
and MN
2
. The first output buffer includes transistors MP
3
and MN
3
. And the second output buffer includes transistors MP
4
and MN
4
. Also, the transistors MP
1
and MP
2
of the first current mirror set have an identical current I which flows through the path
1
constituted by MP
1
and MN
1
, so that the first current mirror set and the second current mirror set can cause an equal current to achieve V
out
={overscore (V)}
out
, as shown in FIG.
1
B. Furthermore, the current by the process will not be influenced, so that the situations in
FIGS. 1D and 1E
will not occur. But this method still has some drawbacks described as followed:
1. Because transistors MP
2
and MN
2
are respectively provided by the first and the second current mirror sets, the gate voltages thereof must have some particular limitations. If the restriction on T
r
/T
f
is necessary, the size of the taper buffer in this method will become larger than conventional one. That's because the gate voltages are respectively not 0 and V
DD
any longer, so as to need a larger current which results in the bigger size of the taper buffer, generally 3~4 times or more.
2. For not interfering with the first and the second current mirrors, the transistors MP
3
, MP
4
, MN
3
, and MN
4
must relatively become larger for controlling the current, generally two times or more of the transistors MP
2
and MN
2
.
3. Because the current of the transistor MP
2
in the current mirror set is larger, the current of the transistor MP
1
will also become larger generally. Thus this method needs more area and power.
Because of the technical defects described above, the applicant keeps on carving unflaggingly to develop a “differential output driver device” through wholehearted experience and research.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a differential output driver device and system for well matching the rise/fall time (T
r
/T
f
, T
r
=T
f
) of the transmission terminal of a differential output driver device and not being interfered by the process.
It is another object of the present invention to provide a differential output driver device and system which are applied to a USB interface for reducing the noise in the process.
In accordance with an aspect of the present invention, a differential output driver for receiving a differential input voltage within a specific range having a first portion of a relatively higher voltage and a second portion of a relatively lower voltage and obtaining an identical voltage variation for output voltages of the first portion and the second portion includes a step-down circuit for receiving the first portion of the relatively higher voltage and lowing the relatively higher voltage to a first output voltage, a step-up circuit for receiving the second potion of the relatively lower voltage and rising the relatively lower voltage to a second output voltage, a first compensation circuit electrically connected to the step-down circuit for providing a first bias to transform the first output voltage into a first compensation voltage, and a second compensation circuit electrically connected to the step-up circuit for providing a second bias to transform the second output voltage into a second compensation voltage, wherein the second compensation voltage and the first compensation voltage have the identical voltage variation value, so as to make the driver generate a periodic output voltage having a substantially regular waveform.
Preferably, the differential output driver is applied to a transmission terminal of a USB (Universal Serial Bus) interface.
Preferably, the first portion of the relatively higher voltage is ranged between 3 and 5 Volts.
Preferably, the second portion of the relatively lower voltage is ranged between 0 and 3 Volts.
Preferably, the step-down circuit includes a first PMOS (P-type Metal-Oxide-Semiconductor) transistor, a first NMOS (N-type Metal-Oxide-Semiconductor) transistor, and a second NMOS transistor.
Certainly, the second NMOS transistor can be a switch.
Certainly the first NMOS includes at least a set of serially connected NMOS transistors.
Certainly, the second NMOS includes at least a set of serially connected NMOS transistors.
Certainly, the first PMOS provides a third bias for cooperating with the relatively higher voltage to actuate the first NMOS transistor to generate the first output voltage by means of a voltage dividing.
Certainly, the third bias can be equivalent to the second bias.
Preferably, the first compensation circuit includes a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.
Certainly, the second PMOS transistor can be a switch.
Certainly, the second PMOS transistor includes at least a set of serially connected PMOS transistors.
Certainly, the third NMOS transistor includes at least a set of serially connected NMOS transistors.
Certainly, the fourth PMOS provides the first bias for cooperating with the first output voltage to actuate the third NMOS transistor to generate the first compensation voltage by means of a voltage dividing.
Preferably, the step-up circuit includes a third PMOS transistor, a fourth PMOS transistor, and a fifth NMOS transistor.
Certainly, the third PMOS transistor can be a switch.
Certainly, the third PMOS transistor includes at least a set of serially connected PMOS transistors.
Certainly, the fourth PMOS transistor includes at least a set of serially connected PMOS transistors.
Certainly, the fifth NMOS provides a fourth bias for cooperating with the relatively lower voltage to actuate the fourth PMOS transistor to generate the second output voltage by means of a voltage dividing.
Certainly, the fourth bias can be equivalent to the first bias.
Preferably, the second compensation circuit includes a fifth PMOS transistor, a sixth PMOS transis

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