Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
1999-12-22
2002-02-26
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S102000
Reexamination Certificate
active
06351407
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of one-time programmable (OTP) non-volatile memory cells, which are likely to keep a programmed state even after the circuit is powered off. The present invention more specifically relates to a differential structure of memory cells, each made from an oxide capacitor.
BACKGROUND OF THE INVENTION
An example of application of OTP cells is the formation of redundancy elements, which are generally provided in memories made in the form of one or several integrated circuit arrays, to functionally replace a defective memory element. The function of the OTP cells then is to program the shifting of the memory rows or columns upon use of a redundancy element to overcome the failure of a column or a row of the array.
In this type of application, either elements fusible, for example, by laser, or OTP memory cells of EEPROM type or of floating-gate transistor type are used. All these conventional structures have the major disadvantage of not being compatible with simple CMOS manufacturing methods. In particular, non-volatile EPROM-type memory cells require two gate oxide thicknesses while a standard CMOS manufacturing method only uses one.
In a standard CMOS method, after forming source and drain regions of P-channel and N-channel MOS transistors in a silicon substrate, a single oxide layer (generally, silicon oxide) and a single polysilicon layer are deposited to form the transistor gates before the metallization levels.
Polysilicon fusible structures are also known, however, which require a strong programming current to obtain the fusion (on the order of 100 mA).
The category of OTP cells to which the present invention applies is generally called an “anti-fuse” structure since the unprogrammed state of the cell is a state of isolation of two electrodes and its programmed state is a state of current flow. The cells are, more specifically, formed of a capacitor formed of an oxide thickness likely to be made conductive (to break down) after application of an overvoltage between the two capacitor electrodes.
A problem which arises in the making of such an oxide breakdown structure with a standard CMOS method is linked to the switching of the high voltage required to break down the capacitors. Indeed, standard transistors cannot switch this high voltage without being, themselves, in a breakdown state.
For example, in a technology where the minimum dimension of a mask pattern is 0.25 &mgr;m, the supply voltage of the CMOS circuits generally is on the order of 2.5 V, while an oxide breakdown OTP cell requires on the order of 10 V for an oxide having a thickness on the order of 5 nm, which is the usual thickness of the gate oxide in this technology.
If such a 10-V voltage generally is available on the integrated circuit boards for which the memory integrated circuits are intended, this voltage is not compatible with addressing selection structures and memory input-output stages, the operating voltage of which is linked to the CMOS method used.
The reading of the content of the memory cells is, however, performed under a low CMOS voltage (for example, 2.5 V). This conventionally results in a need for distinct programming and read circuits due to the very different voltages carried by these circuits. Such distinct circuits are prejudicial to the bulk reduction generally desired for integrated memory circuits.
SUMMARY OF THE INVENTION
The present invention aims at providing a novel differential structure of OTP memory cells, which overcomes the disadvantages of conventional solutions.
The present invention more specifically aims at providing such a differential structure in which the same elements are used, both for the cell programming and reading.
The present invention further aims at providing a structure which is compatible with standard CMOS methods. In particular, the present invention aims at providing a solution which requires no additional step with respect to a conventional CMOS method.
One embodiment of the present invention provides an OTP memory integrated circuit in CMOS technology, including at least two oxide capacitors connected via an unbalanced read transistor to an output stage and forming a differential reading storage element, and a read and programming circuit in which transistors of a first conductivity type are adapted to being used, both during read cycles under a relatively low voltage and during programming cycles under a relatively high voltage, the read transistor being turned on only during read cycles.
According to an embodiment of the present invention, the programming and read circuit includes at least two unbalanced programming transistors of the second conductivity type, the respective drains of which are connected to a first terminal of the capacitors, respectively.
According to an embodiment of the present invention, the programming transistors are, each, associated in series with at least two transistors of the first conductivity type to form at least two first parallel branches between a first supply terminal and the ground, the source of an upper transistor of each branch being connected to the first terminal.
According to an embodiment of the present invention, a second transistor of the first conductivity type of each branch, interposed between the first transistor and the programming transistor, is connected to a terminal of application of an intermediary voltage, smaller than the voltage applied on the first supply terminal.
According to an embodiment of the present invention, the programming and read circuit includes at least two parallel secondary branches, each including, in series between the terminal of application of the intermediary voltage and the ground, at least two transistors of the first conductivity type and one unbalanced programming transistor of the second conductivity type, said first branches including, each, at least three transistors of the first conductivity type.
According to an embodiment of the present invention, the programming transistors are off during read cycles.
According to an embodiment of the present invention, the programming transistors are controlled by complementary signals during a programming cycle.
The foregoing features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 5426614 (1995-06-01), Harward
patent: 5712577 (1998-01-01), Cho
patent: 5815429 (1998-09-01), Sher
patent: 5835402 (1998-11-01), Rao et al.
Jorgenson Lisa
SEED IP Law Group PLLC
STMicroelectronics S.A.
Tarleton E. Russell
Zarabian A.
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