Differential on-line termination

Details Differential on-line termination Differential on-line termination

2008-10-30

2010-06-22

Cho, James (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S027000

Reexamination Certificate

active

07741867

ABSTRACT:
Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals.

REFERENCES:
patent: 6625065 (2003-09-01), Gall
patent: 7092312 (2006-08-01), Choi
patent: 7205788 (2007-04-01), Wang et al.
patent: 7397712 (2008-07-01), Choi
patent: 2001/0035768 (2001-11-01), Garlepp et al.
patent: 2003/0208668 (2003-11-01), To et al.
patent: 2005/0023650 (2005-02-01), Forbes
patent: 2005/0134303 (2005-06-01), Best et al.
patent: 2006/0071683 (2006-04-01), Best et al.
patent: 2006/0261438 (2006-11-01), Forbes
patent: 2007/0139071 (2007-06-01), Nguyen
patent: 2008/0129349 (2008-06-01), Yanbo et al.

Affiliated with

Also associated with

Rating

Differential on-line termination does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Differential on-line termination, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Differential on-line termination will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4183405