Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
1999-04-12
2001-05-01
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S112000
Reexamination Certificate
active
06225830
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to logic circuits, and more particularly to logic gates with improved operating speed and noise properties.
2. Discussion of Related Art
NAND and NOR gates are the basic logic elements used for representing a digital logic circuit in a semiconductor integrated circuit. In general, the logic elements used in a digital logic circuit include AND, OR, NOT, NAND, NOR, XOR and XNOR gates. All these logic elements do not have a different circuit from each other. Instead, a combination of NAND, NOR and NOT gates defines circuits of the other logic elements. For instance, the circuit of an AND gate is defined by connecting, in series, a NOT gate to the output of a NAND gate. The circuit of an OR gate is defined by connecting, in series, a NOT gate to the output of a NOR gate.
FIGS. 1A
,
1
B and
1
C are the logical symbol, truth table, and circuit, respectively, of a related art NAND gate. In FIG.
1
A, A
1
and B
1
are input signals, and Z
1
is an output signal. A logical value of output signal Z
1
is determined by the logical values of the, two input signals A
1
and B
1
.
FIG. 1B
is the truth table of output signal Z
1
based on input signals A
1
and B
1
. When at least one of A
1
and B
1
is 0 (VSS), output signal Z
1
becomes 1 (VDD). On the other hand, when both input signals A
1
and B
1
are
1
, output signal Z
1
becomes 0.
In
FIG. 1C
, two PMOS transistors MP
11
and MP
12
, of which sources are supplied a power supply voltage VDD, are connected in parallel to form a pull-up circuit. The gate of PMOS transistor MP
11
is supplied the first input signal A
1
and the gate of the other PMOS transistor MP
12
is supplied the second input signal B
1
. The drains of the two transistors MP
11
and MP
12
are connected to each other to form a common node.
Two NMOS transistors MN
11
and MN
12
are connected in series between the common node and ground VSS to form a pull-down circuit. The gate of NMOS transistor MN
11
, which is directly connected to the common node, is supplied input signal A
1
and the gate of NMOS transistor MN
12
, which is connected to the ground VSS, is supplied input signal B
1
.
When at least one of the two input signals A
1
and B
1
is 0 (VSS), at least one of the two PMOS transistors MP
11
and MP
12
is turned on, and at least one of the two NMOS transistors MN
11
and MN
12
is turned off. Therefore, output signal Z
1
becomes 1 (VDD). On the other hand, when both input signals A
1
and B
1
are 1, the two PMOS transistors MP
11
and MP
12
are turned off, and the two NMOS transistors MN
11
and MN
12
are turned on. Therefore, output signal Z
1
becomes 0.
FIGS. 2A
,
2
B and
2
C are the logical symbol, truth table, and circuit, respectively, of a related art NOR gate. In
FIG. 2A
, A
2
and B
2
are input signals and Z
2
is an output signal. A logical value of output signal Z
2
is determined by the logical values of the two input signals A
2
and B
2
.
FIG. 2B
is a truth table of output signal Z
2
based on input signals A
2
and B
2
. As shown in the truth table, when at least one of the two input signals A
2
and B
2
is 1, output signal Z
2
becomes 0. On the other hand, if both of the two input signals A
2
and B
2
are 0, output signal Z
2
is 1.
In
FIG. 2C
, two PMOS transistors MP
21
and MP
22
, of which sources are supplied the power supply voltage VDD, are connected in parallel to form a pull-up circuit. The gate of PMOS transistor MP
21
is supplied the input signal A
2
and the gate of PMOS transistor MP
22
is supplied the input signal B
2
. Two NMOS transistors MN
21
and MN
22
are connected in parallel between the drain of PMOS transistor MP
22
and the ground VSS to form a pull-down circuit. The gate of NMOS transistor MN
21
is supplied input signal A
2
and the gate of NMOS transistor MN
22
is supplied input signal B
2
.
When at least one of the two input signals A
2
and B
2
is 1, at least one of the two PMOS transistors MP
21
and MP
22
is turned off, and at least one of the two NMOS transistors MN
21
and MN
22
is turned on. Therefore, output signal Z
2
becomes 0. On the other hand, when both input signals A
2
and B
2
are 0, the two PMOS transistors MP
21
and MP
22
are turned on and the two NMOS transistors MN
21
and MN
22
are turned off. Therefore, output signal Z
2
becomes 1.
As described above, in a NAND gate or a NOR gate of the related art, the output signal fully swings between the levels of the power supply voltage VDD and the ground voltage VSS. Therefore, high-speed operation and low power consumption can not be expected. Also, since the highest levels of the input/output signals are in a single mode, a power supply voltage and ground voltage, if the power supply voltage is varied because of temperature variations, the output signal fails to have a stable logic value. As a result, the reliability of circuit operation is remarkably reduced.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a logic circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a logic circuit having high operation speed and low power consumption.
Another object of the present invention is to reduce chip size by simultaneously representing, for example, a NAND gate and a NOR gate in a logic circuit, and decreasing the number of gates.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
These and other objects are achieved by providing a logic circuit including a first load resistance, a constant current source, and a first logic gate connected between the first load resistance and the constant current source. The first load resistance has a first current driving capability and is connected to a power supply voltage. The constant current source has a second current driving capacity and is connected to ground. The first logic gate performs a first logic operation on received inputs to generate a first output.
These and other objects are also achieved by further providing a second load resistance and a second logic gate. The second load resistance has a third current driving capability and is connected to the power supply voltage. The second logic gate is connected between the second load resistance and the constant current source, and performs a second logic operation on received inputs to generate a second output.
REFERENCES:
patent: 5149992 (1992-09-01), Allstot et al.
patent: 5179358 (1993-01-01), Martin
patent: 5218246 (1993-06-01), Lee et al.
patent: 5254891 (1993-10-01), Dorler et al.
patent: 5568073 (1996-10-01), McClure
patent: 5583456 (1996-12-01), Kimura
patent: 5592107 (1997-01-01), McDermott et al.
patent: 5610539 (1997-03-01), Blauschild et al.
patent: 5920205 (1999-07-01), Bushehki et al.
IEEE International Solid-State Circuits Conference 1996 (2 pages).
Hyundai Electronics Industries Co,. Ltd.
Le Don Phu
Tokar Michael
LandOfFree
Differential mode logic gate having NAND and NOR portions to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Differential mode logic gate having NAND and NOR portions to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Differential mode logic gate having NAND and NOR portions to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2555785