Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-22
2005-11-22
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06968522
ABSTRACT:
A computer-implemented method is disclosed for verifying differential line pair impedance. Properties for a differential line pair segment are read from a circuit design database. Properties of neighboring traces are also from the circuit design database, with the neighboring traces being within a given distance of the differential line pair segment. A modal characteristic impedance of the differential line pair segment is calculated based on the neighboring traces. The differential line pair segment is flagged as having an improper impedance value if the calculated modal characteristic impedance differs from a desired modal characteristic impedance.
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Bois Karl J.
Frank Mark D.
Nelson Jerimy C.
Hewlett--Packard Development Company, L.P.
Tat Binh
Whitmore Stacy A.
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