Differential line pair impedance verification tool

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Reexamination Certificate

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06968522

ABSTRACT:
A computer-implemented method is disclosed for verifying differential line pair impedance. Properties for a differential line pair segment are read from a circuit design database. Properties of neighboring traces are also from the circuit design database, with the neighboring traces being within a given distance of the differential line pair segment. A modal characteristic impedance of the differential line pair segment is calculated based on the neighboring traces. The differential line pair segment is flagged as having an improper impedance value if the calculated modal characteristic impedance differs from a desired modal characteristic impedance.

REFERENCES:
patent: 6381730 (2002-04-01), Chang et al.
patent: 6530062 (2003-03-01), Liaw et al.
patent: 6637008 (2003-10-01), Higuchi et al.
patent: 6769102 (2004-07-01), Frank et al.
patent: 6807650 (2004-10-01), Lamb et al.

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